BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
2 × USA
Collaborated with:
H.Onodera M.Hashimoto Y.Taniguchi
Talks about:
placement (1) techniqu (1) practic (1) reduct (1) layout (1) glitch (1) design (1) consid (1) branch (1) resiz (1)

Person: Keikichi Tamaru

DBLP DBLP: Tamaru:Keikichi

Contributed to:

DAC 19991999
DAC 19911991

Wrote 2 papers:

DAC-1999-HashimotoOT #design #power management #reduction
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design (MH, HO, KT), pp. 446–451.
DAC-1991-OnoderaTT #bound #layout
Branch-and-Bound Placement for Building Block Layout (HO, YT, KT), pp. 433–439.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.