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Travelled to:
1 × China
1 × Germany
2 × USA
Collaborated with:
M.Koibuchi I.Fujiwara H.Amano H.Casanova T.Yoshinaga T.Ozaki R.Kawano S.Tade T.Kagami Y.Take T.Kuroda P.Bogdan R.Marculescu
Talks about:
latenc (4) low (4) chip (3) router (2) random (2) link (2) hpc (2) no (2) interconnect (1) architectur (1)

Person: Hiroki Matsutani

DBLP DBLP: Matsutani:Hiroki

Contributed to:

HPCA 20152015
PDP 20152015
DATE 20142014
HPCA 20132013
HPCA 20092009

Wrote 5 papers:

HPCA-2015-FujiwaraKOMC #network
Augmenting low-latency HPC network with free-space optical links (IF, MK, TO, HM, HC), pp. 390–401.
PDP-2015-KawanoTFMAK
Optimized Core-Links for Low-Latency NoCs (RK, ST, IF, HM, HA, MK), pp. 172–176.
DATE-2014-MatsutaniKFKTKBMA #3d #random
Low-latency wireless 3D NoCs via randomized shortcut chips (HM, MK, IF, TK, YT, TK, PB, RM, HA), pp. 1–6.
HPCA-2013-KoibuchiFMC #random
Layout-conscious random topologies for HPC off-chip interconnects (MK, IF, HM, HC), pp. 484–495.
HPCA-2009-MatsutaniKAY #architecture #latency #predict
Prediction router: Yet another low latency on-chip router architecture (HM, MK, HA, TY), pp. 367–378.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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