Travelled to:
1 × China
1 × Germany
2 × USA
Collaborated with:
H.Matsutani I.Fujiwara H.Amano H.Casanova T.Yoshinaga T.Ozaki A.Shalaby M.E.Ragab V.Goulart R.Kawano S.Tade T.Kagami Y.Take T.Kuroda P.Bogdan R.Marculescu
Talks about:
latenc (4) low (4) chip (3) hpc (3) interconnect (2) network (2) router (2) random (2) link (2) no (2)
Person: Michihiro Koibuchi
DBLP: Koibuchi:Michihiro
Contributed to:
Wrote 6 papers:
- HPCA-2015-FujiwaraKOMC #network
- Augmenting low-latency HPC network with free-space optical links (IF, MK, TO, HM, HC), pp. 390–401.
- PDP-2015-KawanoTFMAK
- Optimized Core-Links for Low-Latency NoCs (RK, ST, IF, HM, HA, MK), pp. 172–176.
- DATE-2014-MatsutaniKFKTKBMA #3d #random
- Low-latency wireless 3D NoCs via randomized shortcut chips (HM, MK, IF, TK, YT, TK, PB, RM, HA), pp. 1–6.
- PDP-2014-ShalabyRGFK #communication #network
- Hierarchical Network Coding for Collective Communication on HPC Interconnects (AS, MESR, VG, IF, MK), pp. 98–102.
- HPCA-2013-KoibuchiFMC #random
- Layout-conscious random topologies for HPC off-chip interconnects (MK, IF, HM, HC), pp. 484–495.
- HPCA-2009-MatsutaniKAY #architecture #latency #predict
- Prediction router: Yet another low latency on-chip router architecture (HM, MK, HA, TY), pp. 367–378.