Travelled to:1 × Germany
1 × Ireland
1 × USA
Collaborated with:S.Roy K.Chakraborty D.Manzi B.Saha X.Zhou Y.Gao S.Yan M.Rajagopalan J.Fang P.Zhang R.Ronen A.Mendelson
Talks about:microprocessor (1) opportunist (1) bottleneck (1) heterogen (1) platform (1) paradigm (1) program (1) pipelin (1) perform (1) exploit (1)
Person: Hu Chen
DBLP: Chen:Hu
Contributed to:
2015
2014
2009Wrote 3 papers:
- DAC-2015-ChenMRC #execution #paradigm #performance
- Opportunistic turbo execution in NTC: exploiting the paradigm shift in performance bottlenecks (HC, DM, SR, KC), p. 6.
- DATE-2014-ChenRC #adaptation #design #named #pipes and filters
- DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors (HC, SR, KC), pp. 1–6.
- PLDI-2009-SahaZCGYRFZRM #framework #platform #programming
- Programming model for a heterogeneous x86 platform (BS, XZ, HC, YG, SY, MR, JF, PZ, RR, AM), pp. 431–440.