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Travelled to:
1 × USA
2 × France
Collaborated with:
D.Dutoit E.Guthmuller A.Sheibanyrad A.Greiner Y.Akgul D.Puschini S.Lesecq E.Beigné P.Benoit L.Torres
Talks about:
power (2) architectur (1) comparison (1) implement (1) asynchron (1) systemat (1) synchron (1) network (1) circuit (1) between (1)

Person: Ivan Miro Panades

DBLP DBLP: Panades:Ivan_Miro

Contributed to:

DAC 20142014
DATE 20132013
DATE 20072007

Wrote 3 papers:

DAC-2014-AkgulPLBPBT #power management
Power management through DVFS and dynamic body biasing in FD-SOI circuits (YA, DP, SL, EB, IMP, PB, LT), p. 6.
DATE-2013-DutoitGP #3d #integration #power management
3D integration for power-efficient computing (DD, EG, IMP), pp. 779–784.
DATE-2007-SheibanyradPG #architecture #comparison #implementation #multi #network
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture (AS, IMP, AG), pp. 1090–1095.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.