Travelled to:1 × USA
4 × Germany
5 × France
Collaborated with:F.Pêcheux A.Andriahantenaina E.Viaud P.Guerrier J.Porquet C.Schwarz Z.Zhang S.Taktak A.Sheibanyrad I.M.Panades A.Mello I.Maia M.Dessouky A.Kaiser M.Louërat L.Lucas F.Wajsbürt L.Winckel M.Hirech O.Florent E.H.Rejouan M.Benabdenbi M.Tuna H.Charlery L.Mortiez C.A.Zeferino L.Burgun N.Dictus E.Pradho C.Sarwary
Talks about:network (5) chip (4) architectur (3) design (3) simul (3) implement (2) compliant (2) parallel (2) complex (2) switch (2)
Person: Alain Greiner
DBLP: Greiner:Alain
Contributed to:
20112010
20082007200620042003200120001994Wrote 13 papers:
- DATE-2011-PorquetGS #architecture #flexibility #memory management #named
- NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs (JP, AG, CS), pp. 591–594.
- DATE-2010-MelloMGP #parallel #simulation
- Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations (AM, IM, AG, FP), pp. 606–609.
- DAC-2008-ZhangGT #2d #algorithm #configuration management #fault tolerance
- A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip (ZZ, AG, ST), pp. 441–446.
- DATE-2007-SheibanyradPG #architecture #comparison #implementation #multi #network
- Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture (AS, IMP, AG), pp. 1090–1095.
- DATE-2006-ViaudPG #modelling #parallel #performance #simulation
- An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles (EV, FP, AG), pp. 94–99.
- DATE-v1-2004-BenabdenbiGPVT #named #testing
- STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores (MB, AG, FP, EV, MT), pp. 712–713.
- DATE-2003-AdriahantenainaCGMZ #named #scalability
- SPIN: A Scalable, Packet Switched, On-Chip Micro-Network (AA, HC, AG, LM, CAZ), pp. 20070–20073.
- DATE-2003-AndriahantenainaG #implementation #network
- Micro-Network for SoC: Implementation of a 32-Port SPIN network (AA, AG), pp. 11128–11129.
- DATE-2001-DessoukyKLG #case study #design #reuse
- Analog design for reuse — case study: very low-voltage sigma-delta modulator (MD, AK, MML, AG), pp. 353–360.
- DATE-2000-GuerrierG #architecture
- A Generic Architecture for On-Chip Packet-Switched Interconnections (PG, AG), pp. 250–256.
- EDAC-1994-BurgunDGPS #complexity #logic #multi #synthesis
- Multilevel Logic Synthesis of Very High Complexity Circuits (LB, ND, AG, EP, CS), p. 669.
- EDAC-1994-GreinerLWW #complexity #design #library
- Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library (AG, LL, FW, LW), pp. 9–13.
- EDAC-1994-HirechFGR #design #simulation #testing
- A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking (MH, OF, AG, EHR), p. 668.