Travelled to:1 × USA
2 × Germany
3 × France
Collaborated with:L.Fesquet G.F.Bouesse F.Germain A.Yakovlev P.Vivet Y.Monnet R.Leveugle C.Piguet T.J.Omnés S.Dumont N.Huot H.Dubreuil J.Rigaud J.Quartana P.Proust J.P.Tual L.Sourgen
Talks about:asynchron (5) circuit (2) system (2) logic (2) high (2) chip (2) architectur (1) transient (1) smartcard (1) principl (1)
Person: Marc Renaudin
DBLP: Renaudin:Marc
Contributed to:
2013
20052005200420022001Wrote 7 papers:
- DATE-2013-YakovlevVR #industrial #logic #roadmap #tool support
- Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools (AY, PV, MR), pp. 1715–1724.
- DAC-2005-MonnetRL #evaluation #fault
- Asynchronous circuits transient faults sensitivity evaluation (YM, MR, RL), pp. 863–868.
- DATE-2005-BouesseRDG #formal method
- DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement (GFB, MR, SD, FG), pp. 424–429.
- DATE-2005-HuotDFR #architecture #logic #multi
- FPGA Architecture for Multi-Style Asynchronous Logic (NH, HD, LF, MR), pp. 32–33.
- DATE-v1-2004-RenaudinBPTSG #security
- High Security Smartcards (MR, GFB, PP, JPT, LS, FG), pp. 228–233.
- DATE-2002-RigaudFRQ #communication #design #modelling
- High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems (JBR, LF, MR, JQ), p. 1090.
- DATE-2001-PiguetRO #power management
- Low-power systems on chips (SOCs) (CP, MR, TJFO), p. 488.