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Travelled to:
1 × France
1 × Germany
1 × The Netherlands
1 × USA
Collaborated with:
A.Raabe C.Buckl A.Knoll H.Ding X.Hu Y.Liu K.Huang J.O.Blech
Talks about:
heterogen (2) network (2) system (2) fault (2) alloc (2) task (2) chip (2) base (2) multiprocessor (1) imperfect (1)

Person: Jia Huang

DBLP DBLP: Huang:Jia

Contributed to:

ECIR 20142014
DAC 20122012
DATE 20122012
DATE 20112011
PDP 20112011

Wrote 5 papers:

ECIR-2014-HuangDHL #approach
A Two-level Approach for Subtitle Alignment (JH, HD, XH, YL), pp. 468–473.
DAC-2012-HuangHRBK #detection #embedded #fault tolerance #towards
Towards fault-tolerant embedded systems with imperfect fault detection (JH, KH, AR, CB, AK), pp. 188–196.
DATE-2012-HuangBRBK #scheduling #smt
Static scheduling of a Time-Triggered Network-on-Chip based on SMT solving (JH, JOB, AR, CB, AK), pp. 509–514.
DATE-2011-HuangRBK #adaptation #runtime #workflow
A workflow for runtime adaptive task allocation on heterogeneous MPSoCs (JH, AR, CB, AK), pp. 1119–1134.
PDP-2011-HuangBRK #energy #multi
Energy-Aware Task Allocation for Network-on-Chip Based Heterogeneous Multiprocessor Systems (JH, CB, AR, AK), pp. 447–454.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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