Travelled to:4 × USA
Collaborated with:M.Roncken C.Salama G.Malecha W.Taha J.Grundy J.Gillenwater A.Y.Zhu R.K.Gupta S.Rawat S.K.Shukla B.Bailey D.K.Beece M.Fujita C.Pixley F.Somenzi
Talks about:verilog (3) synthesiz (2) descript (2) static (2) level (2) check (2) type (2) use (2) interconnect (1) guarante (1)
Person: John O'Leary
DBLP: O'Leary:John
Contributed to:
20092008
2004
2003Wrote 4 papers:
- PEPM-2009-SalamaMTGO #consistency #dependent type #using
- Static consistency checking for verilog wire interconnects: using dependent types to check the sanity of verilog descriptions (CS, GM, WT, JG, JO), pp. 121–130.
- PEPM-2008-GillenwaterMSZTGO #hardware #static typing #using
- Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability (JG, GM, CS, AYZ, WT, JG, JO), pp. 41–50.
- CAV-2004-OLearyR
- Rob Tristan Gerth: 1956?2003 (JO, MR), pp. 1–14.
- DAC-2003-GuptaRSBBFPOS #verification
- Formal verification — prove it or pitch it (RKG, SR, SKS, BB, DKB, MF, CP, JO, FS), pp. 710–711.