BibSLEIGH — Masahiro

Travelled to:

1 × Italy
1 × United Kingdom
13 × USA
2 × France
3 × Germany

Collaborated with:

J.Jain R.Murgai K.Chen R.Mukherjee E.M.Clarke S.P.Rajan B.Chen H.Yoshida I.Ghosh ∅ Y.Matsunaga H.Tanaka V.Boppana K.Takayama Y.Kojima A.M.Gharehbaghi O.Sarbishei B.Alizadeh A.L.Oliveira A.J.Hu M.Yamazaki Y.Lu M.T.Lee Y.Hsu S.Muroga H.Nakamura Y.Kukimoto H.Sato Y.Yasue S.Kono T.Moto-Oka Y.Zhang Z.Peng J.Jiang H.Li A.Biere A.Cimatti Y.Zhu P.Bollineni K.L.McMillan X.Zhao J.Yang J.A.Abraham D.S.Fussell R.K.Gupta S.Rawat S.K.Shukla B.Bailey D.K.Beece C.Pixley J.O'Leary F.Somenzi Yukiyasu Domae Ryosuke Kawanishi Gustavo Alfonso Garcia Ricardez Kenta Kato Koji Shiratsuchi Rintaro Haraguchi Ryosuke Araki H.Fujiyoshi Shuichi Akizuki Manabu Hashimoto Albert J. Causo A.Noda H.Okuda Tsukasa Ogasawara

Talks about:

base (8) use (8) verif (5) circuit (4) model (4) logic (4) level (4) function (3) switch (3) effici (3)

Person: Masahiro Fujita

DBLP: Fujita:Masahiro

Contributed to:

2015

2009

2008

2003

2000

1999

1998

1996

1995

1994

1993

1992

1991

1990

1986

2019

Wrote 25 papers:

DATE-2015-ZhangPJLF #fault #self: Temperature-aware software-based self-testing for delay faults (YZ, ZP, JJ, HL, MF), pp. 423–428.
DAC-2009-FujitaKG #debugging: Debugging from high level down to gate level (MF, YK, AMG), pp. 627–630.
DAC-2009-SarbisheiAF #clustering #heuristic #optimisation #polynomial #using: Polynomial datapath optimization using partitioning and compensation heuristics (OS, BA, MF), pp. 931–936.
DATE-2008-YoshidaF: Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits (HY, MF), pp. 1099–1102.
DAC-2003-GuptaRSBBFPOS #verification: Formal verification — prove it or pitch it (RKG, SR, SKS, BB, DKB, MF, CP, JO, FS), pp. 710–711.
DAC-2000-GhoshF #automation #diagrams #functional #generative #using: Automatic test pattern generation for functional RTL circuits using assignment decision diagrams (IG, MF), pp. 43–48.
DAC-2000-LuJCF #performance #using: Efficient variable ordering using aBDD based sampling (YL, JJ, EMC, MF), pp. 687–692.
CAV-1999-BoppanaRTF #model checking: Model Checking Based on Sequential ATPG (VB, SPR, KT, MF), pp. 418–430.
DAC-1999-BiereCCFZ #model checking #satisfiability #using: Symbolic Model Checking Using SAT Procedures instead of BDDs (AB, AC, EMC, MF, YZ), pp. 317–320.
DAC-1999-BoppanaMJFB #fault #multi: Multiple Error Diagnosis Based on Xlists (VB, RM, JJ, MF, PB), pp. 660–665.
DATE-1999-MukherjeeJTFAF #approach #performance #verification: An Efficient Filter-Based Approach for Combinational Verification (RM, JJ, KT, MF, JAA, DSF), pp. 132–137.
DATE-1999-MurgaiF #on the: On Reducing Transitions Through Data Modifications (RM, MF), p. 82–?.
DAC-1998-MurgaiFO #using: Using Complementation and Resequencing to Minimize Transitions (RM, MF, ALO), pp. 694–697.
FM-1998-FujitaRH #case study #experience #parallel #protocol #verification: Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol (MF, SPR, AJH), pp. 281–295.
CAV-1996-Fujita #verification: Verification of Arithmetic Circuits by Comparing Two Similar Circuits (MF), pp. 159–168.
DAC-1996-LeeHCF #design #modelling #synthesis #using: Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL (MTCL, YCH, BC, MF), pp. 585–590.
DAC-1995-JainMF #learning #verification: Advanced Verification Techniques Based on Learning (JJ, RM, MF), pp. 420–426.
EDAC-1994-ChenYF #debugging #design #identification #model checking: Bug Identification of a Real Chip Design by Symbolic Model Checking (BC, MY, MF), pp. 132–136.
DAC-1993-ClarkeMZFY #scalability: Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping (EMC, KLM, XZ, MF, JY), pp. 54–60.
DAC-1992-ChenF #algorithm #logic #optimisation #performance #set: Efficient Sum-to-One Subsets Algorithm for Logic Optimization (KCC, MF), pp. 443–448.
DAC-1991-ChenMMF #approach #network #optimisation: A Resynthesis Approach for Network Optimization (KCC, YM, SM, MF), pp. 458–463.
CAV-1990-NakamuraKFT #logic #using #verification: A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio (HN, YK, MF, HT), pp. 76–85.
DAC-1990-SatoYMF #diagrams: Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams (HS, YY, YM, MF), pp. 284–289.
ICLP-1986-FujitaKTM86 #compilation #logic programming #named #programming language #prolog: Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog (MF, SK, HT, TMO), pp. 695–709.
CASE-2019-FujitaDKRKSHAFA #multi #using: Bin-picking Robot using a Multi-gripper Switching Strategy based on Object Sparseness (MF, YD, RK, GAGR, KK, KS, RH, RA, HF, SA, MH, AJC, AN, HO, TO), pp. 1540–1547.