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Travelled to:
15 × USA
3 × Germany
8 × France
Collaborated with:
A.Rahimi L.Benini S.K.Shukla J.Li R.Jejurikar A.Dasdan N.D.Dutt A.Nicolau D.Ramanathan S.Gupta F.Doucet S.Irani N.Savoiu Y.Agarwal S.Agrawal C.Pereira A.Marongiu A.Ghofrani K.Cheng T.Weng V.Raghunathan M.B.Srivastava W.Tang S.Y.Liao S.W.K.Tjiang A.Mathur C.J.N.C.Jr. G.D.Micheli M.Otsuka M.Miranda F.Catthoor B.Balaji M.A.A.Faruque D.Cesarini P.Burgio J.Talpin P.L.Guernic M.A.Lastras-Montaño S.Kim J.Coburn A.M.Caulfield A.Akel L.M.Grupp R.Jhala S.Swanson H.V.Antwerpen S.Mohapatra N.Venkatasubramanian R.v.Vignau T.Kam M.Kishinevsky S.Rotem S.Rawat B.Bailey D.K.Beece M.Fujita C.Pixley J.O'Leary F.Somenzi
Talks about:
system (15) level (10) effici (8) embed (8) time (7) design (6) dynam (6) high (6) analysi (5) energi (5)

Person: Rajesh K. Gupta

DBLP DBLP: Gupta:Rajesh_K=

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
DATE 20122012
ASPLOS 20112011
DATE 20112011
DAC 20052005
DAC 20042004
DATE v2 20042004
LCTES 20042004
DAC 20032003
DATE 20032003
DAC 20022002
DATE 20022002
DAC 20012001
DATE 20002000
DAC 19991999
DAC 19981998
DATE 19981998
DAC 19971997
ED&TC 19971997
DAC 19961996
DAC 19921992

Wrote 38 papers:

DAC-2015-BalajiFDGA #abstraction #architecture #cyber-physical #modelling
Models, abstractions, and architectures: the missing links in cyber-physical systems (BB, MAAF, NDD, RKG, YA), p. 6.
DAC-2015-RahimiCMGB #clustering #embedded #hardware #memory management #scheduling #variability
Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters (AR, DC, AM, RKG, LB), p. 6.
DATE-2015-RahimiGCBG #approximate #energy #memory management
Approximate associative memristive memory for energy-efficient GPUs (AR, AG, KTC, LB, RKG), pp. 1497–1502.
DAC-2014-RahimiGLCBG #architecture #collaboration #compilation #energy
Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing (AR, AG, MALM, KTC, LB, RKG), p. 6.
DATE-2014-RahimiBG #energy #fault
Temporal memoization for energy-efficient timing error recovery in GPGPUs (AR, LB, RKG), pp. 1–6.
DAC-2013-RahimiBG #architecture
Aging-aware compiler-directed VLIW assignment for GPGPU architectures (AR, LB, RKG), p. 6.
DATE-2013-RahimiBG #adaptation #approach
Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging (AR, LB, RKG), pp. 1695–1700.
DATE-2013-RahimiMBGB #clustering
Variation-tolerant OpenMP tasking on tightly-coupled processor clusters (AR, AM, PB, RKG, LB), pp. 541–546.
DATE-2012-RahimiBG #analysis
Analysis of instruction-level vulnerability to dynamic voltage and temperature variations (AR, LB, RKG), pp. 1102–1105.
ASPLOS-2011-CoburnCAGGJS #named #performance #persistent
NV-Heaps: making persistent objects fast and safe with next-generation, non-volatile memories (JC, AMC, AA, LMG, RKG, RJ, SS), pp. 105–118.
DATE-2011-AgarwalWG #comprehension
Understanding the role of buildings in a smart microgrid (YA, TW, RKG), pp. 1224–1229.
DAC-2005-JejurikarG #embedded #realtime #scheduling
Dynamic slack reclamation with procrastination scheduling in real-time embedded systems (RJ, RKG), pp. 111–116.
DAC-2004-JejurikarPG #embedded #realtime #scalability
Leakage aware dynamic voltage scaling for real-time embedded systems (RJ, CP, RKG), pp. 275–280.
DATE-v2-2004-AntwerpenDGMPVV #design #energy #multi
Energy-Aware System Design for Wireless Multimedia (HVA, NDD, RKG, SM, CP, NV, RvV), pp. 1124–1131.
LCTES-2004-JejurikarG #realtime #scheduling
Procrastination scheduling in fixed priority real-time systems (RJ, RKG), pp. 57–66.
DAC-2003-GuptaRSBBFPOS #verification
Formal verification — prove it or pitch it (RKG, SR, SKS, BB, DKB, MF, CP, JO, FS), pp. 710–711.
DAC-2003-RaghunathanSG #communication #energy #overview #performance
A survey of techniques for energy efficient on-chip communication (VR, MBS, RKG), pp. 900–905.
DATE-2003-DoucetSG #framework
Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated (FD, SKS, RKG), pp. 10382–10387.
DATE-2003-GuptaDGN #branch #design #synthesis
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs (SG, NDD, RKG, AN), pp. 10270–10275.
DATE-2003-TalpinGSGD #design
Polychrony for Refinement-Based Design (JPT, PLG, SKS, RKG, FD), pp. 11172–11173.
DAC-2002-GuptaSDGNKKR #coordination #performance #synthesis
Coordinated transformations for high-level synthesis of high performance microprocessor blocks (SG, NS, NDD, RKG, AN, TK, MK, SR), pp. 898–903.
DATE-2002-DoucetSGO #co-evolution #component #composition #design #performance
An Environment for Dynamic Component Composition for Efficient Co-Design (FD, SKS, RKG, MO), pp. 736–743.
DATE-2002-IraniGS #analysis #multi #power management
Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States (SI, RKG, SKS), pp. 117–123.
DATE-2002-SavoiuSG #automation #concurrent #modelling #performance #simulation
Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation (NS, SKS, RKG), pp. 875–881.
DATE-2002-TangGN #embedded #power management
Power Savings in Embedded Processors through Decode Filer Cache (WT, RKG, AN), pp. 443–448.
DAC-2001-GuptaSKDGN #design #synthesis
Speculation Techniques for High Level Synthesis of Control Intensive Designs (SG, NS, SK, NDD, RKG, AN), pp. 269–272.
DATE-2000-GuptaGMC #analysis #program transformation #programmable
Analysis of High-Level Address Code Transformations for Programmable Processors (SG, RKG, MM, FC), pp. 9–13.
DATE-2000-RamanathanG #algorithm #online #power management
System Level Online Power Management Algorithms (DR, RKG), pp. 606–611.
DAC-1999-DasdanIG #algorithm #performance #problem
Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio Problems (AD, SI, RKG), pp. 37–42.
DAC-1998-DasdanRG #embedded #realtime
Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems (AD, DR, RKG), pp. 263–268.
DATE-1998-LiG #algorithm #behaviour
An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions (JL, RKG), pp. 457–463.
DAC-1997-AgrawalG #behaviour #clustering #data flow #embedded
Data-Flow Assisted Behavioral Partitioning for Embedded Systems (SA, RKG), pp. 709–712.
DAC-1997-LiG #exception #modelling #optimisation
Limited Exception Modeling and Its Use in Presynthesis Optimizations (JL, RKG), pp. 341–346.
DAC-1997-LiaoTG #design #hardware #implementation #modelling #performance
An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment (SYL, SWKT, RKG), pp. 70–75.
EDTC-1997-DasdanMG #analysis #constraints #debugging #embedded #named
RATAN: A tool for rate analysis and rate constraint debugging for embedded systems (AD, AM, RKG), pp. 2–6.
DAC-1996-Gupta #analysis #constraints #embedded #execution
Analysis of Operation Delay and Execution Rate Constraints for Embedded Systems (RKG), pp. 601–604.
DAC-1996-LiG #optimisation #using
HDL Optimization Using Timed Decision Tables (JL, RKG), pp. 51–54.
DAC-1992-GuptaCM #component #hardware #simulation #synthesis
Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components (RKG, CJNCJ, GDM), pp. 225–230.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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