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Travelled to:
7 × USA
Collaborated with:
∅ K.Chung R.J.Francis I.Kuon Z.G.Vranesic M.D.Hutton J.P.Grossman D.G.Corneil
Talks about:
technolog (3) map (3) architectur (2) parallel (2) circuit (2) router (2) lookup (2) global (2) explor (2) chortl (2)

Person: Jonathan Rose

DBLP DBLP: Rose:Jonathan

Contributed to:

DAC 20082008
DAC 19961996
DAC 19921992
DAC 19911991
DAC 19901990
DAC 19881988
PPEALS 19881988

Wrote 7 papers:

DAC-2008-KuonR #architecture #automation
Automated transistor sizing for FPGA architecture exploration (IK, JR), pp. 792–795.
DAC-1996-HuttonGRC #generative #random
Characterization and Parameterized Random Generation of Digital Circuits (MDH, JPG, JR, DGC), pp. 94–99.
DAC-1992-ChungR #architecture #named
TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections (KC, JR), pp. 361–367.
DAC-1991-FrancisRV #named #performance
Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs (RJF, JR, ZGV), pp. 227–233.
DAC-1990-FrancisRC #array #named #programmable
Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays (RJF, JR, KC), pp. 613–619.
DAC-1988-Rose #named #parallel #standard
LocusRoute: A Parallel Global Router for Standard Cells (JR), pp. 189–195.
PPEALS-1988-Rose #composition #implementation #parallel
The Parallel Decomposition and Implementation of an Integrated Circuit Global Router (JR), pp. 138–145.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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