Travelled to:1 × USA
2 × France
Collaborated with:A.Rueda S.Mir D.Vázquez J.A.Prieto J.M.Quintana T.Olbrich E.J.Peralías
Talks about:switch (4) capacitor (2) system (2) level (2) fault (2) placement (1) algorithm (1) swittest (1) simultan (1) perform (1)
Person: José Luis Huertas
DBLP: Huertas:Jos=eacute=_Luis
Contributed to:
1998
19971997Wrote 3 papers:
- DATE-1998-MirRVH #analysis #fault
- Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems (SM, AR, DV, JLH), pp. 810–814.
- DAC-1997-MirROPH #automation #evaluation #fault #named #simulation
- SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems (SM, AR, TO, EJP, JLH), pp. 281–286.
- EDTC-1997-PrietoRQH #algorithm #optimisation
- A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs (JAP, AR, JMQ, JLH), pp. 389–394.