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Travelled to:
1 × USA
4 × France
5 × Germany
Collaborated with:
H.D.Stratigopoulos J.Tongbong J.Carbonéro A.Bounceur A.Rueda J.L.Huertas K.Huang Y.Makris L.Abdallah J.Altet A.Dhayni L.Rufer R.Kheriji V.Danelon L.Rolíndez G.Prenat D.Vázquez T.Olbrich E.J.Peralías
Talks about:
test (8) switch (4) fault (3) evalu (3) base (3) capacitor (2) circuit (2) system (2) machin (2) analog (2)

Person: Salvador Mir

DBLP DBLP: Mir:Salvador

Contributed to:

DATE 20122012
DATE 20102010
DATE 20092009
DATE 20082008
DATE 20072007
DATE 20062006
DATE 20052005
DATE v1 20042004
DATE 19981998
DAC 19971997

Wrote 10 papers:

DATE-2012-AbdallahSMA #testing
Testing RF circuits with true non-intrusive built-in sensors (LA, HGDS, SM, JA), pp. 1090–1095.
DATE-2010-HuangSM #fault #machine learning
Fault diagnosis of analog circuits based on machine learning (KH, HGDS, SM), pp. 1761–1766.
DATE-2009-StratigopoulosMM #set
Enrichment of limited training sets in machine-learning-based analog/RF test (HGDS, SM, YM), pp. 1668–1673.
DATE-2008-StratigopoulosTM #estimation #parametricity
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation (HGDS, JT, SM), pp. 68–73.
DATE-2007-TongbongMC #evaluation #interactive #metric #multi #statistics #testing #using
Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model (JT, SM, JLC), pp. 731–736.
DATE-2006-DhayniMRB #functional #linear #pseudo
Pseudorandom functional BIST for linear and nonlinear MEMS (AD, SM, LR, AB), pp. 664–669.
DATE-2005-KherijiDCM #approach #optimisation #testing
Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach (RK, VD, JLC, SM), pp. 170–171.
DATE-v1-2004-RolindezMPB #generative #implementation
A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns (LR, SM, GP, AB), pp. 706–707.
DATE-1998-MirRVH #analysis #fault
Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems (SM, AR, DV, JLH), pp. 810–814.
DAC-1997-MirROPH #automation #evaluation #fault #named #simulation
SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems (SM, AR, TO, EJP, JLH), pp. 281–286.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.