Travelled to:1 × USA
2 × Germany
5 × France
Collaborated with:E.J.Peralías D.Vázquez G.Leger J.L.Huertas J.L.Huertas A.J.Ginés A.J.Acosta N.M.Madrid S.Mir J.A.Prieto M.J.B.Asian J.M.Quintana G.Huertas R.Seepold T.Olbrich I.A.Grout A.M.D.Richardson
Talks about:analog (5) switch (4) signal (4) design (4) fault (3) test (3) mix (3) methodolog (2) capacitor (2) pipelin (2)
Person: Adoración Rueda
DBLP: Rueda:Adoraci=oacute=n
Contributed to:
200820042002200120001998
19971997Wrote 11 papers:
- DATE-2008-AsianVR #implementation #network
- Practical Implementation of a Network Analyzer for Analog BIST Applications (MJBA, DV, AR), pp. 80–85.
- DATE-v1-2004-GinesPR #fault #pipes and filters
- Digital Background Gain Error Correction in Pipeline ADCs (AJG, EJP, AR), pp. 82–87.
- DATE-v1-2004-LegerR #first-order
- A Digital Test for First-Order [Sigma-Delta] Modulators (GL, AR), pp. 708–709.
- DATE-v1-2004-VazquezLHRH #parametricity #self
- A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications (DV, GL, GH, AR, JLH), pp. 298–305.
- DATE-2002-GinesPRSM #behaviour #design #modelling #parametricity #reuse
- A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects (AJG, EJP, AR, RS, NMM), pp. 310–314.
- DATE-2001-MadridPAR #design #modelling #reuse
- Analog/mixed-signal IP modeling for design reuse (NMM, EJP, AJA, AR), pp. 766–767.
- DATE-2000-PeraliasARH #design #pipes and filters #verification
- A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters (EJP, AJA, AR, JLH), pp. 534–538.
- DATE-1998-MirRVH #analysis #fault
- Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems (SM, AR, DV, JLH), pp. 810–814.
- DATE-1998-PrietoRGPHR #approach #design #fault #layout #predict #testing
- An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits (JAP, AR, IAG, EJP, JLH, AMDR), pp. 905–909.
- DAC-1997-MirROPH #automation #evaluation #fault #named #simulation
- SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems (SM, AR, TO, EJP, JLH), pp. 281–286.
- EDTC-1997-PrietoRQH #algorithm #optimisation
- A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs (JAP, AR, JMQ, JLH), pp. 389–394.