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Travelled to:
3 × USA
Collaborated with:
E.G.Friedman Y.I.Ismail
Talks about:
character (1) schedul (1) process (1) equival (1) variat (1) induct (1) import (1) toler (1) optim (1) merit (1)

Person: José Luis Neves

DBLP DBLP: Neves:Jos=eacute=_Luis

Contributed to:

DAC 19991999
DAC 19981998
DAC 19961996

Wrote 3 papers:

DAC-1999-IsmailFN
Equivalent Elmore Delay for RLC Trees (YII, EGF, JLN), pp. 715–720.
DAC-1998-IsmailFN
Figures of Merit to Characterize the Importance of On-Chip Inductance (YII, EGF, JLN), pp. 560–565.
DAC-1996-NevesF #process #scheduling
Optimal Clock Skew Scheduling Tolerant to Process Variations (JLN, EGF), pp. 623–628.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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