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Travelled to:
1 × China
1 × Germany
1 × Ireland
1 × Italy
1 × The Netherlands
10 × USA
Collaborated with:
C.E.Oancea J.Torrellas N.M.Amato Y.Zhang J.Huang A.Jula S.Saunders H.Yu D.Patel D.A.Padua Harshvardhan T.G.Smith D.Tomkins G.Tanase N.Thomas O.Tkachyshyn J.Perdue M.J.Garzarán M.Prvulovic J.M.Llabería V.Viñals A.A.Buss A.Fidel I.Papadopoulos O.Pearce X.Xu N.Mourad J.Vu M.Bianco
Talks about:
parallel (11) specul (5) time (4) loop (4) run (4) multiprocessor (3) algorithm (3) memori (3) framework (2) techniqu (2)

Person: Lawrence Rauchwerger

DBLP DBLP: Rauchwerger:Lawrence

Contributed to:

CGO 20152015
ESEC/FSE 20152015
PPoPP 20152015
PPoPP 20142014
PLDI 20122012
PPoPP 20112011
ISMM 20092009
PPoPP 20052005
HPCA 20032003
PPoPP 20032003
CC 20002000
CC 19991999
HPCA 19991999
HPCA 19981998
PLDI 19951995

Wrote 15 papers:

CGO-2015-OanceaR #analysis #induction #scalability
Scalable conditional induction variables (CIV) analysis (CEO, LR), pp. 213–224.
ESEC-FSE-2015-HuangR #branch
Finding schedule-sensitive branches (JH, LR), pp. 439–449.
PPoPP-2015-HarshvardhanAR #algorithm #approach #communication #graph #parallel
A hierarchical approach to reducing communication in parallel graph algorithms (H, NMA, LR), pp. 285–286.
PPoPP-2014-TomkinsSAR #algorithm #component #named #parallel
SCCMulti: an improved parallel strongly connected components algorithm (DT, TGS, NMA, LR), pp. 393–394.
PLDI-2012-OanceaR #logic #parallel
Logical inference techniques for loop parallelization (CEO, LR), pp. 509–520.
PPoPP-2011-TanaseBFHPPSTXMVBAR #framework #parallel
The STAPL parallel container framework (GT, AAB, AF, H, IP, OP, TGS, NT, XX, NM, JV, MB, NMA, LR), pp. 235–246.
ISMM-2009-JulaR #locality #memory management
Two memory allocators that use hints to improve locality (AJ, LR), pp. 109–118.
PPoPP-2005-ThomasTTPAR #adaptation #algorithm #framework
A framework for adaptive algorithm selection in STAPL (NT, GT, OT, JP, NMA, LR), pp. 277–288.
HPCA-2003-GarzaranPLVRT #concurrent #memory management #multi #thread #trade-off
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors (MJG, MP, JML, VV, LR, JT), pp. 191–202.
PPoPP-2003-SaundersR #adaptation #communication #framework #independence #library #named #platform
ARMI: an adaptive, platform independent communication library (SS, LR), pp. 230–241.
CC-2000-YuR #parallel #runtime
Techniques for Reducing the Overhead of Run-Time Parallelization (HY, LR), pp. 232–248.
CC-1999-PatelR #implementation #parallel #runtime
Implementation Issues of Loop-Level Speculative Run-Time Parallelization (DP, LR), pp. 183–197.
HPCA-1999-ZhangRT #hardware #parallel
Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors (YZ, LR, JT), pp. 135–139.
HPCA-1998-ZhangRT #distributed #hardware #parallel #runtime
Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors (YZ, LR, JT), pp. 162–173.
PLDI-1995-RauchwergerP #parallel #reduction #runtime
The LRPD Test: Speculative Run-Time Parallelization of Loops with Privatization and Reduction Parallelization (LR, DAP), pp. 218–232.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.