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Travelled to:
1 × India
7 × USA
Collaborated with:
I.Doudalis G.Venkataramani Y.Solihin ∅ S.Subramaniam G.H.Loh J.Oh C.J.Hughes J.A.Clause A.Orso B.Roemer B.Rogers C.Yan S.Chhabra M.Kharbutli X.Jiang M.J.Garzarán J.M.Llabería V.Viñals L.Rauchwerger J.Torrellas
Talks about:
memori (5) protect (3) taint (3) multiprocessor (2) programm (2) thread (2) execut (2) effici (2) effect (2) level (2)

Person: Milos Prvulovic

DBLP DBLP: Prvulovic:Milos

Contributed to:

ICSE 20112011
HPCA 20102010
HPCA 20082008
ASE 20072007
HPCA 20072007
ASPLOS 20062006
HPCA 20062006
HPCA 20032003

Wrote 10 papers:

ICSE-2011-OhHVP #concurrent #debugging #execution #framework #multi #named #thread
LIME: a framework for debugging load imbalance in multi-threaded execution (JO, CJH, GV, MP), pp. 201–210.
HPCA-2010-DoudalisP #execution #hardware #named
HARE: Hardware assisted reverse execution (ID, MP), pp. 1–12.
HPCA-2008-RogersYCPS #distributed #memory management #multi
Single-level integrity and confidentiality protection for distributed shared memory multiprocessors (BR, CY, SC, MP, YS), pp. 161–172.
HPCA-2008-SubramaniamPL #dependence #memory management #named #predict #smt
PEEP: Exploiting predictability of memory dependences in SMT processors (SS, MP, GHL), pp. 137–148.
HPCA-2008-VenkataramaniDSP #named #programmable
FlexiTaint: A programmable accelerator for dynamic taint propagation (GV, ID, YS, MP), pp. 173–184.
ASE-2007-ClauseDOP #effectiveness #memory management #using
Effective memory protection using dynamic tainting (JAC, ID, AO, MP), pp. 284–292.
HPCA-2007-VenkataramaniRSP #debugging #memory management #monitoring #named #performance #programmable
MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging (GV, BR, YS, MP), pp. 273–284.
ASPLOS-2006-KharbutliJSVP
Comprehensively and efficiently protecting the heap (MK, XJ, YS, GV, MP), pp. 207–218.
HPCA-2006-Prvulovic #concurrent #detection #effectiveness #named
CORD: cost-effective (and nearly overhead-free) order-recording and data race detection (MP), pp. 232–243.
HPCA-2003-GarzaranPLVRT #concurrent #memory management #multi #thread #trade-off
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors (MJG, MP, JML, VV, LR, JT), pp. 191–202.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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