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Travelled to:
1 × France
Collaborated with:
A.Calimera A.Macii E.Macii M.Poncino
Talks about:
industri (1) concurr (1) design (1) power (1) enabl (1) clock (1) gate (1) flow (1)

Person: Letícia Maria Veiras Bolzani

DBLP DBLP: Bolzani:Let=iacute=cia_Maria_Veiras

Contributed to:

DATE 20092009

Wrote 1 papers:

DATE-2009-BolzaniCMMP #concurrent #design #industrial #power management
Enabling concurrent clock and power gating in an industrial design flow (LMVB, AC, AM, EM, MP), pp. 334–339.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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