BibSLEIGH — Massimo

Travelled to:

11 × France
11 × USA
9 × Germany

Collaborated with:

E.Macii A.Macii L.Benini A.Calimera M.Loghi F.Fummi G.Perbellini S.Martini R.Scarsi G.D.Micheli D.Shin H.Mahmood M.Monguzzi L.Macchiarulo V.Tenace S.Miryala F.Ferrandi G.Odasso G.D.Hachtel F.Somenzi A.V.Sathanur P.Azzoni F.Ricciato K.Patel G.Castelli S.Rinaudo A.Acquaviva M.Otella M.Sciolla O.Golubeva A.Sassone M.Montazeri G.Gangemi W.Liu A.Nannarelli L.M.V.Bolzani N.Drago D.Sciuto H.Cho Y.Wang Q.Xie M.Pedram Y.Kim N.Chang A.Pullini A.Chakraborty P.Sithambaram K.Duraisami M.Turolla E.Omerbegovic F.Pro P.Gallo A.Lioy S.Manne A.Pardo R.I.Bahar V.Guarnieri M.Petricca S.Vinco N.Bombieri R.Goldman V.Melikyan E.Babayan

Talks about:

power (15) system (9) energi (9) architectur (8) optim (8) base (8) network (7) memori (7) synthesi (6) partit (6)

Person: Massimo Poncino

DBLP: Poncino:Massimo

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

1997

1996

1995

1994

Wrote 47 papers:

DAC-2015-TenaceCMP #logic #synthesis: One-pass logic synthesis for graphene-based Pass-XNOR logic circuits (VT, AC, EM, MP), p. 6.
DAC-2014-ShinMP #modelling #statistics: Statistical Battery Models and Variation-Aware Battery Management (DS, EM, MP), p. 6.
DATE-2014-GuarnieriPSVBFMP #embedded #monitoring #verification: A cross-level verification methodology for digital IPs augmented with embedded timing monitors (VG, MP, AS, SV, NB, FF, EM, MP), pp. 1–6.
DATE-2014-MahmoodPM #performance #reduction #using: Cache aging reduction with improved performance using dynamically re-sizable cache (HM, MP, EM), pp. 1–6.
DATE-2014-ShinPM #architecture #hybrid #using: Thermal management of batteries using a hybrid supercapacitor architecture (DS, MP, EM), pp. 1–6.
DATE-2014-TenaceCMP #logic: Pass-XNOR logic: A new logic style for P-N junction based graphene circuits (VT, AC, EM, MP), pp. 1–4.
DAC-2013-CalimeraMP #constraints #energy #fault #scheduling: Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints (AC, EM, MP), p. 6.
DATE-2013-MiryalaMCMP #configuration management #logic: A verilog-a model for reconfigurable logic gates based on graphene pn-junctions (SM, MM, AC, EM, MP), pp. 877–880.
DATE-2012-MahmoodPLM #clustering #energy #memory management #optimisation: Application-specific memory partitioning for joint energy and lifetime optimization (HM, MP, ML, EM), pp. 364–369.
DATE-2012-MiryalaCMP #analysis #network: IR-drop analysis of graphene-based power distribution networks (SM, AC, EM, MP), pp. 81–86.
DATE-2012-SassoneCMMPGMBR #dependence #network: Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks (AS, AC, AM, EM, MP, RG, VM, EB, SR), pp. 165–166.
DATE-2012-WangXPKCP #energy #hybrid #migration #multi: Multiple-source and multiple-destination charge migration in hybrid electrical energy storage systems (YW, QX, MP, YK, NC, MP), pp. 169–174.
DATE-2011-AcquavivaPOS #power management #reliability: System level techniques to improve reliability in high power microcontrollers for automotive applications (AA, MP, MO, MS), pp. 1123–1124.
DATE-2011-CalimeraLMP #architecture: Partitioned cache architectures for reduced NBTI-induced aging (AC, ML, EM, MP), pp. 938–943.
DATE-2011-RinaudoGCMP #approach #design #energy #performance #power management: Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems (SR, GG, AC, AM, MP), pp. 1127–1128.
DATE-2010-LiuNCMP #reduction: Post-placement temperature reduction techniques (WL, AN, AC, EM, MP), pp. 634–637.
DATE-2009-BolzaniCMMP #concurrent #design #industrial #power management: Enabling concurrent clock and power gating in an industrial design flow (LMVB, AC, AM, EM, MP), pp. 334–339.
DATE-2008-SathanurPBMMP #algorithm #framework #scalability: A Scalable Algorithmic Framework for Row-Based Power-Gating (AVS, AP, LB, AM, EM, MP), pp. 379–384.
DATE-2007-GolubevaLPM #architecture: Architectural leakage-aware management of partitioned scratchpad memories (OG, ML, MP, EM), pp. 1665–1670.
DATE-2007-SathanurCBMMP #bound #clustering #interactive #performance: Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing (AVS, AC, LB, AM, EM, MP), pp. 1544–1549.
DATE-2006-ChakrabortySDMMP #bound #optimisation: Thermal resilient bounded-skew clock tree optimization methodology (AC, PS, KD, AM, EM, MP), pp. 832–837.
DATE-2005-FummiLMMPP #hardware #prototype: Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation (FF, ML, SM, MM, GP, MP), pp. 798–803.
DATE-2005-LoghiAP #architecture #energy: Tag Overflow Buffering: An Energy-Efficient Cache Architecture (ML, PA, MP), pp. 520–525.
DATE-2005-LoghiP #energy #memory management #performance #trade-off: Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions (ML, MP), pp. 508–513.
DATE-DF-2004-FummiMMPP #analysis #architecture #industrial #modelling #network: Modeling and Analysis of Heterogeneous Industrial Networks Architectures (FF, SM, MM, GP, MP), pp. 342–344.
DATE-DF-2004-FummiMPPRT #embedded: Heterogeneous Co-Simulation of Networked Embedded Systems (FF, SM, GP, MP, FR, MT), pp. 168–173.
DATE-v1-2004-FummiMPP #integration #multi: Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC (FF, SM, GP, MP), pp. 564–569.
DATE-v1-2004-PatelMP #architecture #energy #memory management #multi #synthesis: Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC (KP, EM, MP), pp. 700–701.
DAC-2003-BeniniMMOPP #analysis #design #difference #energy: Energy-aware design techniques for differential power analysis protection (LB, AM, EM, EO, FP, MP), pp. 36–41.
DAC-2003-FummiPGPMR #embedded #modelling #simulation: A timing-accurate modeling and simulation environment for networked embedded systems (FF, GP, PG, MP, SM, FR), pp. 42–47.
DATE-2003-DragoFMPP #architecture #embedded #estimation #performance #tuple: Estimation of Bus Performance for a Tuplespace in an Embedded Architecture (ND, FF, MM, GP, MP), pp. 20188–20195.
DATE-2003-MaciiMP #clustering #memory management #performance: Improving the Efficiency of Memory Partitioning by Address Clustering (AM, EM, MP), pp. 10018–10023.
DATE-2002-MacchiaruloMP #energy: Wire Placement for Crosstalk Energy Minimization in Address Buses (LM, EM, MP), pp. 158–162.
DAC-2001-BeniniMMMP #architecture #embedded #layout #memory management #synthesis: From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip (LB, LM, AM, EM, MP), pp. 784–789.
DATE-2001-BeniniCMMPS #scheduling: Extending lifetime of portable systems by battery scheduling (LB, GC, AM, EM, MP, RS), pp. 197–203.
DAC-2000-BeniniMMP #embedded #optimisation #synthesis: Synthesis of application-specific memories for power optimization in embedded systems (LB, AM, EM, MP), pp. 300–303.
DATE-2000-BeniniCMMPS #estimation: A Discrete-Time Battery Model for High-Level Power Estimation (LB, GC, AM, EM, MP, RS), pp. 35–39.
DAC-1999-BeniniMMOP #algorithm #approximate #component #kernel #optimisation: Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms (LB, GDM, EM, GO, MP), pp. 247–252.
DAC-1999-BeniniMMPS #communication #interface #power management #synthesis: Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses (LB, AM, EM, MP, RS), pp. 128–133.
DATE-1999-BeniniMMMPS #power management: Glitch Power Minimization by Gate Freezing (LB, GDM, AM, EM, MP, RS), pp. 163–167.
DAC-1998-BeniniMLMOP #kernel #optimisation: Computational Kernels and their Application to Sequential Power Optimization (LB, GDM, AL, EM, GO, MP), pp. 764–769.
DATE-1998-FerrandiFMP #behaviour #estimation: Power Estimation of Behavioral Descriptions (FF, FF, EM, MP), pp. 762–766.
DAC-1997-BeniniMP #adaptation #design #latency #pipes and filters #throughput: Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control (LB, EM, MP), pp. 22–27.
EDTC-1997-BeniniMMPS #logic #network #optimisation #synthesis: Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks (LB, GDM, EM, MP, RS), pp. 514–520.
DAC-1996-FerrandiFMPS #automaton #network #optimisation: Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques (FF, FF, EM, MP, DS), pp. 467–470.
DAC-1995-MannePBHSMP: Computing the Maximum Power Cycles of a Sequential Circuit (SM, AP, RIB, GDH, FS, EM, MP), pp. 23–28.
EDAC-1994-ChoHMPS #algorithm #approximate #automaton #composition #traversal: A State Space Decomposition Algorithm for Approximate FSM Traversal (HC, GDH, EM, MP, FS), pp. 137–141.