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Travelled to:
1 × Germany
1 × USA
Collaborated with:
A.Janapsatya S.Parameswaran J.Peddersen H.Javaid
Talks about:
processor (2) approach (2) replac (2) polici (2) simul (2) embed (2) fast (2) cach (2) pipelin (1) runtim (1)

Person: Mohammad Shihabul Haque

DBLP DBLP: Haque:Mohammad_Shihabul

Contributed to:

DAC 20102010
DATE 20102010

Wrote 3 papers:

DAC-2010-HaquePJP #approach #embedded #named #performance #policy #simulation
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy (MSH, JP, AJ, SP), pp. 356–361.
DATE-2010-HaquePJP #approach #embedded #named #performance #policy #simulation
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy (MSH, JP, AJ, SP), pp. 496–501.
DATE-2010-JavaidJHP #agile #estimation #pipes and filters #runtime
Rapid runtime estimation methods for pipelined MPSoCs (HJ, AJ, MSH, SP), pp. 363–368.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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