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Travelled to:
1 × France
2 × Germany
5 × USA
Collaborated with:
S.Parameswaran M.Shafique J.Henkel H.Bokhari H.C.Doan S.M.Min I.Nawinne J.Schneider A.Janapsatya M.S.Haque Y.Yachide S.M.M.Shwe X.Zhang J.Peddersen
Talks about:
pipelin (5) chip (3) silicon (2) network (2) hardwar (2) specif (2) explor (2) energi (2) design (2) applic (2)

Person: Haris Javaid

DBLP DBLP: Javaid:Haris

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DAC 20112011
DATE 20102010
DAC 20092009

Wrote 11 papers:

DAC-2015-BokhariJSHP #architecture #manycore #named
SuperNet: multimode interconnect architecture for manycore chips (HB, HJ, MS, JH, SP), p. 6.
DATE-2015-BokhariJSHP #adaptation
Malleable NoC: dark silicon inspired adaptable Network-on-Chip (HB, HJ, MS, JH, SP), pp. 1245–1248.
DATE-2015-ZhangJSPHP #hardware #manycore #named #pipes and filters
E-pipeline: elastic hardware/software pipelines on a many-core fabric (XZ, HJ, MS, JP, JH, SP), pp. 363–368.
DAC-2014-BokhariJSHP #design #energy #multi #named
darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon (HB, HJ, MS, JH, SP), p. 6.
DAC-2014-JavaidYSBP #component #framework #metric #named
FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs (HJ, YY, SMMS, HB, SP), p. 6.
DATE-2014-DoanJP #flexibility #implementation #multi #scalability #using
Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs (HCD, HJ, SP), pp. 1–6.
DATE-2014-NawinneSJP #performance
Hardware-based fast exploration of cache hierarchies in application specific MPSoCs (IN, JS, HJ, SP), pp. 1–6.
DAC-2013-MinJP #energy #named #optimisation #reduction
XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs (SMM, HJ, SP), p. 10.
DAC-2011-JavaidSPH #adaptation #case study #multi #pipes and filters #power management #video
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study (HJ, MS, SP, JH), pp. 1032–1037.
DATE-2010-JavaidJHP #agile #estimation #pipes and filters #runtime
Rapid runtime estimation methods for pipelined MPSoCs (HJ, AJ, MSH, SP), pp. 363–368.
DAC-2009-JavaidP #design #multi #pipes and filters
A design flow for application specific heterogeneous pipelined multiprocessor systems (HJ, SP), pp. 250–253.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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