Travelled to:1 × Cyprus
1 × France
1 × Germany
2 × USA
Collaborated with:S.Parameswaran A.Janapsatya M.S.Haque J.Schneider K.Avnit A.Sowmya A.Ignjatovic X.Zhang H.Javaid M.Shafique J.Henkel
Talks about:cach (5) replac (3) polici (3) simul (3) fifo (3) processor (2) approach (2) pipelin (2) hardwar (2) embed (2)
Person: Jorgen Peddersen
DBLP: Peddersen:Jorgen
Contributed to:
2015
201420102010
2010Wrote 6 papers:
- DATE-2015-ZhangJSPHP #hardware #manycore #named #pipes and filters
- E-pipeline: elastic hardware/software pipelines on a many-core fabric (XZ, HJ, MS, JP, JH, SP), pp. 363–368.
- DAC-2014-SchneiderPP #agile #analysis #multi
- MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis (JS, JP, SP), p. 6.
- DAC-2010-HaquePJP #approach #embedded #named #performance #policy #simulation
- SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy (MSH, JP, AJ, SP), pp. 356–361.
- DATE-2010-HaquePJP #approach #embedded #named #performance #policy #simulation
- DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy (MSH, JP, AJ, SP), pp. 496–501.
- DATE-2010-JanapsatyaIPP #adaptation #algorithm #policy
- Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm (AJ, AI, JP, SP), pp. 920–925.
- TACAS-2010-AvnitSP #automation #named #protocol #synthesis
- ACS: Automatic Converter Synthesis for SoC Bus Protocols (KA, AS, JP), pp. 343–348.