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Travelled to:
10 × USA
5 × France
7 × Germany
Collaborated with:
H.Javaid J.Henkel R.G.Ragel M.Shafique J.Peddersen A.Janapsatya J.A.Ambrose J.Schneider Y.J.Chong K.Patel H.Bokhari M.S.Haque T.Li L.Tang N.Cheung A.Ignjatovic S.L.Shee S.Radhakrishnan H.C.Doan S.M.Min H.Guo V.E.Boros A.D.Rakic S.Rehman A.Kumar I.Nawinne J.Chan Y.Yachide S.M.M.Shwe K.Avnit V.D'Silva A.Sowmya S.Ramesh X.Zhang
Talks about:
processor (8) pipelin (8) cach (8) hardwar (6) specif (6) applic (6) base (6) instruct (5) rapid (5) embed (5)

Person: Sri Parameswaran

DBLP DBLP: Parameswaran:Sri

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
DATE 20122012
DAC 20112011
DAC 20102010
DATE 20102010
DAC 20092009
DATE 20092009
DAC 20082008
DATE 20082008
DAC 20072007
DATE 20072007
DAC 20062006
DATE 20062006
DATE v2 20042004
DATE 20032003
DATE 20012001
DAC 20002000

Wrote 35 papers:

DAC-2015-BokhariJSHP #architecture #manycore #named
SuperNet: multimode interconnect architecture for manycore chips (HB, HJ, MS, JH, SP), p. 6.
DATE-2015-BokhariJSHP #adaptation
Malleable NoC: dark silicon inspired adaptable Network-on-Chip (HB, HJ, MS, JH, SP), pp. 1245–1248.
DATE-2015-TangAKP #communication #configuration management
Dynamic reconfigurable puncturing for secure wireless communication (LT, JAA, AK, SP), pp. 888–891.
DATE-2015-ZhangJSPHP #hardware #manycore #named #pipes and filters
E-pipeline: elastic hardware/software pipelines on a many-core fabric (XZ, HJ, MS, JP, JH, SP), pp. 363–368.
DAC-2014-BokhariJSHP #design #energy #multi #named
darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon (HB, HJ, MS, JH, SP), p. 6.
DAC-2014-JavaidYSBP #component #framework #metric #named
FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs (HJ, YY, SMMS, HB, SP), p. 6.
DAC-2014-SchneiderPP #agile #analysis #multi
MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis (JS, JP, SP), p. 6.
DATE-2014-DoanJP #flexibility #implementation #multi #scalability #using
Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs (HCD, HJ, SP), pp. 1–6.
DATE-2014-NawinneSJP #performance
Hardware-based fast exploration of cache hierarchies in application specific MPSoCs (IN, JS, HJ, SP), pp. 1–6.
DAC-2013-LiSARHP #adaptation #embedded #fault #named #runtime
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors (TL, MS, JAA, SR, JH, SP), p. 7.
DAC-2013-MinJP #energy #named #optimisation #reduction
XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs (SMM, HJ, SP), p. 10.
DAC-2013-TangAP #communication #configuration management #multi #pipes and filters
Reconfigurable pipelined coprocessor for multi-mode communication transmission (LT, JAA, SP), p. 8.
DATE-2013-LiSRRRAHP #configuration management #named
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors (TL, MS, SR, SR, RGR, JAA, JH, SP), pp. 707–712.
DATE-2013-SchneiderP #adaptation #embedded
An extremely compact JPEG encoder for adaptive embedded systems (JS, SP), pp. 1063–1064.
DATE-2012-LiRP #embedded #hardware #named
Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors (TL, RGR, SP), pp. 875–880.
DAC-2011-JavaidSPH #adaptation #case study #multi #pipes and filters #power management #video
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study (HJ, MS, SP, JH), pp. 1032–1037.
DAC-2010-HaquePJP #approach #embedded #named #performance #policy #simulation
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy (MSH, JP, AJ, SP), pp. 356–361.
DATE-2010-HaquePJP #approach #embedded #named #performance #policy #simulation
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy (MSH, JP, AJ, SP), pp. 496–501.
DATE-2010-JanapsatyaIPP #adaptation #algorithm #policy
Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm (AJ, AI, JP, SP), pp. 920–925.
DATE-2010-JavaidJHP #agile #estimation #pipes and filters #runtime
Rapid runtime estimation methods for pipelined MPSoCs (HJ, AJ, MSH, SP), pp. 363–368.
DAC-2009-JavaidP #design #multi #pipes and filters
A design flow for application specific heterogeneous pipelined multiprocessor systems (HJ, SP), pp. 250–253.
DATE-2009-PatelPR #architecture #framework #named #security
CUFFS: An instruction count based architectural framework for security of MPSoCs (KP, SP, RGR), pp. 779–784.
DAC-2008-ChongP #agile #float #generative
Rapid application specific floating-point unit generation with bit-alignment (YJC, SP), pp. 62–67.
DAC-2008-PatelP #design #hardware #named #reliability #security
SHIELD: a software hardware design methodology for security and reliability of MPSoCs (KP, SP), pp. 858–861.
DATE-2008-AvnitDSRP #approach #formal method #problem #protocol
A Formal Approach To The Protocol Converter Problem (KA, VD, AS, SR, SP), pp. 294–299.
DAC-2007-AmbroseRP #analysis #injection #named #random
RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks (JAA, RGR, SP), pp. 489–492.
DAC-2007-SheeP #design #multi #pipes and filters
Design Methodology for Pipelined Heterogeneous Multiprocessor System (SLS, SP), pp. 811–816.
DATE-2007-ChongP #automation #float #generative
Automatic application specific floating-point unit generation (YJC, SP), pp. 461–466.
DATE-2007-JanapsatyaIPH #agile #simulation
Instruction trace compression for rapid instruction cache simulation (AJ, AI, SP, JH), pp. 803–808.
DAC-2006-RagelP #monitoring #named #reliability #security
IMPRES: integrated monitoring for processor reliability and security (RGR, SP), pp. 502–505.
DATE-2006-RadhakrishnanGP #multi
Customization of application specific heterogeneous multi-pipeline processors (SR, HG, SP), pp. 746–751.
DATE-v2-2004-CheungPHC #equivalence #named #using
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor (NC, SP, JH, JC), pp. 1020–1027.
DATE-2003-CheungHP #agile #case study
Rapid Configuration and Instruction Selection for an ASIP: A Case Study (NC, JH, SP), pp. 10802–10809.
DATE-2001-Parameswaran #hardware #performance
Code placement in hardware/software co-synthesis to improve performance and reduce cost (SP), pp. 626–632.
DAC-2000-BorosRP #configuration management #multi
High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system (VEB, ADR, SP), pp. 221–226.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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