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Travelled to:
1 × Germany
1 × USA
Collaborated with:
G.Qu K.Usami M.Potkonjak T.Kitahara F.Minami K.Seta T.Furusawa
Talks about:
methodolog (2) power (2) microprocessor (1) threshold (1) function (1) standbi (1) select (1) reduct (1) leakag (1) effici (1)

Person: Naoyuki Kawabe

DBLP DBLP: Kawabe:Naoyuki

Contributed to:

DATE 20052005
DAC 20002000

Wrote 2 papers:

DATE-2005-KitaharaKMSF #design #multi #power management #reduction
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction (TK, NK, FM, KS, TF), pp. 646–647.
DAC-2000-QuKUP #estimation
Function-level power estimation methodology for microprocessors (GQ, NK, KU, MP), pp. 810–813.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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