Travelled to:
1 × France
Collaborated with:
C.Weis M.Jung C.Santos P.Vivet S.Goossens M.Koedam N.Wehn
Talks about:
retent (1) measur (1) model (1) error (1) wide (1) time (1) rate (1) dram (1) bit (1)
Person: Peter Ehses
DBLP: Ehses:Peter
Contributed to:
Wrote 1 papers:
- DATE-2015-Weis0ESVGKW #fault #metric #modelling
- Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs (CW, MJ, PE, CS, PV, SG, MK, NW), pp. 495–500.