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Travelled to:
1 × France
Collaborated with:
C.Weis M.Jung C.Santos P.Vivet S.Goossens M.Koedam N.Wehn
Talks about:
retent (1) measur (1) model (1) error (1) wide (1) time (1) rate (1) dram (1) bit (1)

Person: Peter Ehses

DBLP DBLP: Ehses:Peter

Contributed to:

DATE 20152015

Wrote 1 papers:

DATE-2015-Weis0ESVGKW #fault #metric #modelling
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs (CW, MJ, PE, CS, PV, SG, MK, NW), pp. 495–500.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.