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Travelled to:
3 × France
3 × Germany
Collaborated with:
F.Clermidy D.Dutoit A.Yakovlev M.Renaudin J.J.H.Pontes N.Calazans Y.Thonnart F.Beneventi A.Bartolini L.Benini C.Helmstetter J.Cornet B.Galilée M.Moy F.Darve W.Lafi C.Weis M.Jung P.Ehses C.Santos S.Goossens M.Koedam N.Wehn T.Sassolas C.Sandionigi A.Guerre A.Aminot H.Boussetta L.Ferro N.Peltier
Talks about:
design (3) asynchron (2) thermal (2) model (2) logic (2) accur (2) dram (2) gal (2) no (2) architectur (1)

Person: Pascal Vivet

DBLP DBLP: Vivet:Pascal

Contributed to:

DATE 20152015
DATE 20142014
DATE 20132013
DATE 20122012
DATE 20112011
DATE 20102010

Wrote 8 papers:

DATE-2015-Weis0ESVGKW #fault #metric #modelling
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs (CW, MJ, PE, CS, PV, SG, MK, NW), pp. 495–500.
DATE-2014-BeneventiBVDB #analysis #identification #logic
Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip (FB, AB, PV, DD, LB), pp. 1–4.
DATE-2014-SassolasSGAVBFP #architecture #design #evaluation
Early design stage thermal evaluation and mitigation: The locomotiv architectural case (TS, CS, AG, AA, PV, HB, LF, NP), pp. 1–2.
DATE-2013-HelmstetterCGMV #performance #simulation #using
Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications (CH, JC, BG, MM, PV), pp. 1185–1188.
DATE-2013-YakovlevVR #industrial #logic #roadmap #tool support
Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools (AY, PV, MR), pp. 1715–1724.
DATE-2012-PontesCV #design #reliability
An accurate Single Event Effect digital design flow for reliable system level design (JJHP, NC, PV), pp. 224–229.
DATE-2011-ClermidyDDLV #3d #embedded #manycore
3D Embedded multi-core: Some perspectives (FC, FD, DD, WL, PV), pp. 1327–1332.
DATE-2010-ThonnartVC #framework #integration #power management
A fully-asynchronous low-power framework for GALS NoC integration (YT, PV, FC), pp. 33–38.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.