Travelled to:1 × USA
2 × Germany
3 × France
Collaborated with:N.Wehn L.Benini B.Akesson K.Goossens K.Chandrasekar I.Loi M.Jung S.Goossens M.Koedam D.Bortolotti A.Bartolini D.Rossi M.Sadri M.D.Gomony P.Ehses C.Santos P.Vivet
Talks about:dram (8) system (3) energi (3) power (3) wide (3) time (3) variat (2) effici (2) stack (2) optim (2)
Person: Christian Weis
DBLP: Weis:Christian
Contributed to:
20152014
2013201320122011Wrote 9 papers:
- DATE-2015-Weis0ESVGKW #fault #metric #modelling
- Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs (CW, MJ, PE, CS, PV, SG, MK, NW), pp. 495–500.
- DATE-2014-0001GWKAWG #optimisation #performance #runtime
- Exploiting expendable process-margins in DRAMs for run-time performance optimization (KC, SG, CW, MK, BA, NW, KG), pp. 1–6.
- DATE-2014-BortolottiBWRB #architecture #hybrid #manycore #memory management #power management #scalability
- Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors (DB, AB, CW, DR, LB), pp. 1–6.
- DATE-2014-Sadri0WWB #3d #energy #optimisation #using
- Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh (MS, MJ, CW, NW, LB), pp. 1–4.
- DAC-2013-0001WAWG #approach #empirical #estimation #towards
- Towards variation-aware system-level power estimation of DRAMs: an empirical approach (KC, CW, BA, NW, KG), p. 8.
- DATE-2013-0001WAWG #3d #energy #modelling
- System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs (KC, CW, BA, NW, KG), pp. 236–241.
- DATE-2012-GomonyWAWG #mobile #realtime
- DRAM selection and configuration for real-time mobile systems (MDG, CW, BA, NW, KG), pp. 51–56.
- DATE-2012-WeisLBW #3d #energy #performance
- An energy efficient DRAM subsystem for 3D integrated SoCs (CW, IL, LB, NW), pp. 1138–1141.
- DATE-2011-WeisWLB #3d #design
- Design space exploration for 3D-stacked DRAMs (CW, NW, IL, LB), pp. 389–394.