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Travelled to:
1 × France
1 × USA
Collaborated with:
N.Vijaykrishnan S.Bae S.Srinivasan Y.Xie K.Sarpatwari
Talks about:
fpga (2) schedul (1) lifetim (1) exploit (1) clock (1) skew (1) flaw (1) awar (1)

Person: Prasanth Mangalagiri

DBLP DBLP: Mangalagiri:Prasanth

Contributed to:

DATE 20092009
DAC 20062006

Wrote 2 papers:

DATE-2009-BaeMV #scheduling
Exploiting clock skew scheduling for FPGA (SB, PM, NV), pp. 1524–1529.
DAC-2006-SrinivasanMXVS #named
FLAW: FPGA lifetime awareness (SS, PM, YX, NV, KS), pp. 630–635.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.