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Travelled to:
1 × Austria
1 × Belgium
1 × Italy
1 × Mexico
1 × Spain
14 × USA
3 × Canada
5 × France
5 × Germany
Collaborated with:
M.J.Irwin M.T.Kandemir A.Sivasubramaniam J.S.Hu Y.Xie G.Chen I.Kadayif M.Mutyam N.Ranganathan G.M.Link H.Saputra A.J.Ricketts L.K.John L.Li D.Duarte P.Mangalagiri A.Gayasen S.Srinivasan W.Zhang Y.Tsai H.S.Kim W.Ye S.Eachempati C.R.Das V.Delaluz F.Li J.Ramanujam Y.Massoud S.Kim T.Li S.Bae M.Wolczko R.Gadekarla N.Bhavanishankar R.R.Brooks S.Gurumurthi K.M.Irick F.Wang R.Radhakrishnan A.Rathi M.DeBole W.Ge R.T.Collins J.Singh K.Ramakrishnan D.K.Pradhan R.Das A.K.Mishra A.Nieuwoudt K.Sarpatwari J.Kim D.Park T.Theocharides W.Hung S.Yang W.Wolf D.N.Serpanos V.De J.Rubio V.Degalahal B.Mathiske R.Shetty A.Parikh T.Chinoda N.An M.Mondal S.Kirolos T.Ragheb C.Hsu U.Kremer
Talks about:
energi (10) power (8) compil (7) interconnect (6) architectur (6) schedul (6) chip (6) awar (6) optim (5) java (5)

Person: Narayanan Vijaykrishnan

DBLP DBLP: Vijaykrishnan:Narayanan

Contributed to:

DATE 20102010
DATE 20092009
HPCA 20092009
DATE 20072007
DAC 20062006
DATE 20062006
LCTES 20062006
DAC 20052005
DATE 20052005
DATE v1 20042004
HPCA 20042004
ISMM 20042004
LCTES 20042004
DAC 20032003
DATE 20032003
LCTES 20032003
OOPSLA 20032003
ASPLOS 20022002
DAC 20022002
DATE 20022002
HPCA 20022002
DAC 20012001
HPCA 20012001
LCTES/OM 20012001
PASTE 20012001
VLDB 20012001
DAC 20002000
HPCA 20002000
LCTES 20002000
ECOOP 19981998
ICPR 19961996

Wrote 49 papers:

DATE-2010-RathiDGCV #distance #feature model #gpu #implementation
A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching (AR, MD, WG, RTC, NV), pp. 172–177.
DATE-2010-RickettsSRVP #power management
Investigating the impact of NBTI on different power saving cache strategies (AJR, JS, KR, NV, DKP), pp. 592–597.
DATE-2009-BaeMV #scheduling
Exploiting clock skew scheduling for FPGA (SB, PM, NV), pp. 1524–1529.
HPCA-2009-DasEMVD #design #evaluation
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs (RD, SE, AKM, NV, CRD), pp. 175–186.
DATE-2007-EachempatiNGVM #architecture
Assessing carbon nanotube bundle interconnect for future FPGA architectures (SE, AN, AG, NV, YM), pp. 307–312.
DATE-2007-MondalRKRLVM #3d #robust
Thermally robust clocking schemes for 3D integrated circuits (MM, AJR, SK, TR, GML, NV, YM), pp. 1206–1211.
DATE-2007-MutyamV #process
Working with process variation aware caches (MM, NV), pp. 1152–1157.
DAC-2006-SrinivasanMXVS #named
FLAW: FPGA lifetime awareness (SS, PM, YX, NV, KS), pp. 630–635.
DATE-2006-RickettsIVI #scheduling
Priority scheduling in digital microfluidics-based biochips (AJR, KMI, NV, MJI), pp. 329–334.
DATE-2006-WangXVI #analysis #optimisation
On-chip bus thermal analysis and optimization (FW, YX, NV, MJI), pp. 850–855.
LCTES-2006-MutyamLNKI #functional
Compiler-directed thermal management for VLIW functional units (MM, FL, NV, MTK, MJI), pp. 163–172.
Exploring technology alternatives for nano-scale FPGA interconnects (AG, NV, MJI), pp. 921–926.
DAC-2005-KimPTVD #adaptation #latency
A low latency router supporting adaptivity for on-chip interconnects (JK, DP, TT, NV, CRD), pp. 559–564.
DATE-2005-HuLDKVI #detection #fault
Compiler-Directed Instruction Duplication for Soft Error Detection (JSH, FL, VD, MTK, NV, MJI), pp. 1056–1057.
DATE-2005-HungXVKI #embedded #scheduling
Thermal-Aware Task Allocation and Scheduling for Embedded Systems (WLH, YX, NV, MTK, MJI), pp. 898–899.
DATE-2005-LinkV #configuration management #runtime
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip (GML, NV), pp. 648–649.
DATE-2005-SrinivasanLV #architecture #clustering
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures (SS, LL, NV), pp. 218–223.
DATE-2005-TsaiVXI #network
Leakage-Aware Interconnect for On-Chip Network (YFT, NV, YX, MJI), pp. 230–231.
DATE-2005-YangWVSX #approach #design
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach (SY, WW, NV, DNS, YX), pp. 64–69.
DATE-v1-2004-HuVKKI #reduction #reuse #scheduling
Scheduling Reusable Instructions for Power Reduction (JSH, NV, SK, MTK, MJI), pp. 148–155.
A Crosstalk Aware Interconnect with Variable Cycle Transmission (LL, NV, MTK, MJI), pp. 102–107.
HPCA-2004-HuVI #scheduling
Exploring Wakeup-Free Instruction Scheduling (JSH, NV, MJI), pp. 232–243.
ISMM-2004-ChenKVI #analysis #embedded #java #optimisation
Field level analysis for heap space optimization in embedded java environments (GC, MTK, NV, MJI), pp. 131–142.
LCTES-2004-SaputraCBVKI #embedded
Code protection for resource-constrained embedded devices (HS, GC, RRB, NV, MTK, MJI), pp. 240–248.
DAC-2003-TsaiDVI #reduction #scalability
Implications of technology scaling on leakage reduction techniques (YFT, DD, NV, MJI), pp. 187–190.
DATE-2003-SaputraVKIBKZ #behaviour #encryption #energy
Masking the Energy Behavior of DES Encryption (HS, NV, MTK, MJI, RRB, SK, WZ), pp. 10084–10089.
DATE-2003-ZhangKVID #compilation #energy
Compiler Support for Reducing Leakage Energy Consumption (WZ, MTK, NV, MJI, VD), pp. 11146–11147.
LCTES-2003-KimVKI #adaptation #architecture #optimisation #parallel
Adapting instruction level parallelism for optimizing leakage in VLIW architectures (HSK, NV, MTK, MJI), pp. 275–283.
OOPSLA-2003-ChenKVIMW #java
Heap compression for memory-constrained Java environments (GC, MTK, NV, MJI, BM, MW), pp. 282–301.
ASPLOS-2002-LiJSVR #comprehension #control flow #operating system #predict
Understanding and improving operating system effects in control flow prediction (TL, LKJ, AS, NV, JR), pp. 68–80.
DAC-2002-DelaluzSKVI #energy
Scheduler-based DRAM energy management (VD, AS, MTK, NV, MJI), pp. 697–702.
DATE-2002-DuarteVI #power management
A Complete Phase-Locked Loop Power Consumption Model (DD, NV, MJI), p. 1108.
DATE-2002-HuVKI #power management
Power-Efficient Trace Caches (JSH, NV, MTK, MJI), p. 1091.
DATE-2002-KadayifKVIS #compilation #energy #estimation #framework #named #optimisation
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization (IK, MTK, NV, MJI, AS), pp. 436–442.
HPCA-2002-ChenSKVIW #embedded #garbage collection #java
Tuning Garbage Collection in an Embedded Java Environment (GC, RS, MTK, NV, MJI, MW), pp. 92–103.
HPCA-2002-GurumurthiSIVKLJ #approach #estimation #simulation #using
Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach (SG, AS, MJI, NV, MTK, TL, LKJ), pp. 141–150.
LCTES-SCOPES-2002-HuKVISZ #morphism #polymorphism
Compiler-directed cache polymorphism (JSH, MTK, NV, MJI, HS, WZ), pp. 165–174.
LCTES-SCOPES-2002-SaputraKVIHHK #compilation #energy #scalability
Energy-conscious compilation based on voltage scaling (HS, MTK, NV, MJI, JSH, CHH, UK), pp. 2–11.
DAC-2001-KandemirRIVKP #memory management
Dynamic Management of Scratch-Pad Memory Space (MTK, JR, MJI, NV, IK, AP), pp. 690–695.
HPCA-2001-DelaluzKVSI #energy #hardware #using
DRAM Energy Management Using Software and Hardware Directed Power Mode Control (VD, MTK, NV, AS, MJI), pp. 159–169.
LCTES-OM-2001-KadayifKVIR #architecture
Morphable Cache Architectures: Potential Benefits (IK, MTK, NV, MJI, JR), pp. 128–137.
PASTE-2001-KadayifCKVIS #energy #named
vEC: virtual energy counters (IK, TC, MTK, NV, MJI, AS), pp. 28–31.
VLDB-2001-AnSVKIG #behaviour #data access #energy
Analyzing energy behavior of spatial access methods for memory-resident data (NA, AS, NV, MTK, MJI, SG), pp. 411–420.
DAC-2000-KandemirVIY #compilation #optimisation
Influence of compiler optimizations on system power (MTK, NV, MJI, WY), pp. 304–307.
DAC-2000-YeVKI #design #energy #estimation #using
The design and use of simplepower: a cycle-accurate energy estimation tool (WY, NV, MTK, MJI), pp. 340–345.
HPCA-2000-RadhakrishnanVJS #architecture #java #runtime
Architectural Issues in Java Runtime Systems (RR, NV, LKJ, AS), pp. 387–398.
LCTES-2000-KandemirVIK #energy #towards
Towards Energy-Aware Iteration Space Tiling (MTK, NV, MJI, HSK), pp. 211–215.
ECOOP-1998-VijaykrishnanRG #architecture #java #object-oriented
Object-Oriented Architectural Support for a Java Processor (NV, NR, RG), pp. 330–354.
ICPR-1996-RanganathanBV #array #image #linear
A dynamic frequency linear array processor for image processing (NR, NB, NV), pp. 611–615.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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