BibSLEIGH — Yuan

Travelled to:

1 × China
1 × India
12 × USA
6 × France
7 × Germany

Collaborated with:

X.Dong G.Sun C.Xu W.Wolf N.Vijaykrishnan J.Zhao M.J.Irwin Y.Chen F.Wang J.Wang D.Niu Y.Wang J.Zhan H.Yang T.Zhang V.Narayanan N.P.Jouppi M.T.Kandemir J.Li X.Wu Q.Zou Y.Chen J.Ouyang X.Chen M.Poremba N.Muralimanohar G.Chen H.Ju C.H.Lin H.Lekatsas Y.Joo C.R.Das S.Li J.Sampson X.Hu E.Kursun Y.Tsai F.Ge M.Poremba S.Mittal D.Li J.S.Vetter Y.Liang Z.Wang D.A.Jiménez W.Wen Y.Zhang L.Zhang E.Speight S.Srinivasan P.Mangalagiri K.Sarpatwari W.Hung S.Tosun N.Mansouri E.Arvas S.Yang D.N.Serpanos Y.Liu X.Li K.Ma H.Cheng Y.Xu J.Ma Y.Hu W.Liu X.Han N.Stoimenov L.Thiele Y.Chang Y.S.Huang C.King Y.Chen S.Eachempati C.Wang S.Datta S.Srikantaiah E.Kultursay N.Chang W.Wang Y.Cao H.H.Li H.Luo K.He R.Luo R.Balasubramonian S.Yu A.Jog A.K.Mishra R.Iyer R.Das H.Li Y.Zheng K.Swaminathan Ling Liang Lei Deng 0003 Pengfei Zuo Yu Ji 0002 Xinfeng Xie Y.Ding C.Liu T.Sherwood Z.Li H.Li Y.Wang M.Chang S.John J.Shu

Talks about:

cach (13) design (11) awar (11) architectur (7) memori (7) level (7) ram (7) energi (6) power (5) chip (5)

Person: Yuan Xie

DBLP: Xie:Yuan

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2001

2020

Wrote 49 papers:

DAC-2015-ChengZZ0SI: Core vs. uncore: the heart of darkness (HYC, JZ, JZ, YX, JS, MJI), p. 6.
DAC-2015-LiuLLWLMLCJ0SY #energy: Ambient energy harvesting nonvolatile processors: from circuit to system (YL, ZL, HL, YW, XL, KM, SL, MFC, SJ, YX, JS, HY), p. 6.
DAC-2015-ZhanOGZ0 #approach #named #network #power management #towards: DimNoC: a dim silicon approach towards power-efficient on-chip network (JZ, JO, FG, JZ, YX), p. 6.
DATE-2015-PorembaMLVX #3d #modelling #named: DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches (MP, SM, DL, JSV, YX), pp. 1543–1546.
HPCA-2015-MaZLSLLS0N #architecture #energy: Architecture exploration for ambient energy harvesting nonvolatile processors (KM, YZ, SL, KS, XL, YL, JS, YX, VN), pp. 526–537.
HPCA-2015-XuNMBZY0 #architecture #challenge #memory management: Overcoming the challenges of crossbar resistive memory architectures (CX, DN, NM, RB, TZ, SY, YX), pp. 476–488.
DAC-2014-ChenWLXY #optimisation #runtime: Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs (XC, YW, YL, YX, HY), p. 6.
DAC-2014-HuXMCHX #thread: Thermal-Sustainable Power Budgeting for Dynamic Threading (XH, YX, JM, GC, YH, YX), p. 6.
DAC-2014-LiuCHWXY #3d #design: Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case (WL, GC, XH, YW, YX, HY), p. 6.
DAC-2014-ZhanXS #fine-grained #named: NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era (JZ, YX, GS), p. 6.
HPCA-2014-WangJXSX #adaptation #hybrid #migration #policy: Adaptive placement and migration policy for an STT-RAM-based hybrid cache (ZW, DAJ, CX, GS, YX), pp. 13–24.
HPCA-2014-ZhangPXSX #architecture #memory management #named: CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture (TZ, MP, CX, GS, YX), pp. 368–379.
DAC-2013-XuNMJX #comprehension #design #memory management #multi #trade-off: Understanding the trade-offs in multi-level cell ReRAM memory design (CX, DN, NM, NPJ, YX), p. 6.
DAC-2013-ZhanSOTNX #design #embedded #energy #optimisation #realtime: Designing energy-efficient NoC for real-time embedded systems through slack optimization (JZ, NS, JO, LT, VN, YX), p. 6.
DATE-2013-WangDX #named #policy: OAP: an obstruction-aware cache management policy for STT-RAM last-level caches (JW, XD, YX), pp. 847–852.
DATE-2013-ZouZKX #3d #design: Thermomechanical stress-aware management for 3D IC designs (QZ, TZ, EK, YX), pp. 1255–1258.
HPCA-2013-ChangHPNXK #named #network: TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network (YYC, YSCH, MP, VN, YX, CTK), pp. 390–399.
HPCA-2013-WangDXJ #named: i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations (JW, XD, YX, NPJ), pp. 234–245.
DAC-2012-JogMXXNID #architecture #performance: Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs (AJ, AKM, CX, YX, VN, RI, CRD), pp. 243–252.
DAC-2012-WangDX #architecture: Point and discard: a hard-error-tolerant architecture for non-volatile last level caches (JW, XD, YX), pp. 253–258.
DAC-2012-WenZCWX #analysis #named #performance #reliability #scalability #statistics: PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method (WW, YZ, YC, YW, YX), pp. 1191–1196.
DATE-2012-ChenSZX #3d #named #physics #synthesis: 3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs (YC, GS, QZ, YX), pp. 1185–1190.
DATE-2012-SunXX #design #memory management #modelling: Modeling and design exploration of FBDRAM as on-chip memory (GS, CX, YX), pp. 1507–1512.
DAC-2011-ChenEWDXN #array #automation #configuration management: Automated mapping for reconfigurable single-electron transistor arrays (YCC, SE, CYW, SD, YX, VN), pp. 878–883.
DATE-2011-XuDJX #design: Design implications of memristor-based RRAM cross-point structures (CX, XD, NPJ, YX), pp. 734–739.
DATE-2011-ZhaoDX #3d #design #energy #fine-grained #scalability: An energy-efficient 3D CMP design with fine-grained voltage scaling (JZ, XD, YX), pp. 539–542.
HPCA-2011-SrikantaiahKZKIX #adaptation #configuration management #multi #named: MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy (SS, EK, TZ, MTK, MJI, YX), pp. 231–242.
DAC-2010-NiuCXX #process: Impact of process variations on emerging memristor (DN, YC, CX, YX), pp. 877–882.
DAC-2010-WuSDDXDL #3d #integration: Cost-driven 3D integration with interconnect layers (XW, GS, XD, RD, YX, CRD, JL), pp. 150–155.
DAC-2010-ZhaoDX #3d #cost analysis #design #manycore: Cost-aware three-dimensional (3D) many-core multiprocessor design (JZ, XD, YX), pp. 126–131.
DATE-2010-JooNDSCX #design #energy #memory management: Energy- and endurance-aware design of phase change memory caches (YJ, DN, XD, GS, NC, YX), pp. 136–141.
HPCA-2010-SunJCNXCL #architecture #energy #hybrid #performance: A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement (GS, YJ, YC, DN, YX, YC, HL), pp. 1–12.
DATE-2009-0002CWCXY #optimisation: Gate replacement techniques for simultaneous leakage and aging optimization (YW, XC, WW, YC, YX, HY), pp. 328–333.
DATE-2009-WuLZSX #hybrid #performance: Power and performance of read-write aware Hybrid Caches with non-volatile memories (XW, JL, LZ, ES, YX), pp. 737–742.
HPCA-2009-SunDXLC #3d #architecture #novel: A novel architecture of the 3D stacked MRAM L2 cache for CMPs (GS, XD, YX, JL, YC), pp. 239–249.
DAC-2008-DongWSXLC #3d #architecture #evaluation #memory management #ram: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement (XD, XW, GS, YX, HHL, YC), pp. 554–559.
DATE-2008-WangSX #framework #synthesis: A Variation Aware High Level Synthesis Framework (FW, GS, YX), pp. 1063–1068.
DATE-2007-0004XJ #analysis #novel #statistics: A novel criticality computation method in statistical timing analysis (FW, YX, HJ), pp. 1611–1616.
DATE-2007-WangLHLYX #modelling #performance: Temperature-aware NBTI modeling and the impact of input vector control on performance degradation (YW, HL, KH, RL, HY, YX), pp. 546–551.
DAC-2006-SrinivasanMXVS #named: FLAW: FPGA lifetime awareness (SS, PM, YX, NV, KS), pp. 630–635.
DATE-2006-WangXVI #analysis #optimisation: On-chip bus thermal analysis and optimization (FW, YX, NV, MJI), pp. 850–855.
DATE-2005-HungXVKI #embedded #scheduling: Thermal-Aware Task Allocation and Scheduling for Embedded Systems (WLH, YX, NV, MTK, MJI), pp. 898–899.
DATE-2005-TosunMAKX #synthesis: Reliability-Centric High-Level Synthesis (ST, NM, EA, MTK, YX), pp. 1258–1263.
DATE-2005-TsaiVXI #network: Leakage-Aware Interconnect for On-Chip Network (YFT, NV, YX, MJI), pp. 230–231.
DATE-2005-YangWVSX #approach #design: Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach (SY, WW, NV, DNS, YX), pp. 64–69.
DATE-DF-2004-LinXW #embedded: LZW-Based Code Compression for VLIW Embedded Systems (CHL, YX, WW), pp. 76–81.
DATE-2003-XieWL: Profile-Driven Selective Code Compression (YX, WW, HL), pp. 10462–10467.
DATE-2001-XieW #graph #hardware #scheduling: Allocation and scheduling of conditional task graph in hardware/software co-synthesis (YX, WW), pp. 620–625.
ASPLOS-2020-HuLL0Z0XDLSX #architecture #framework #learning #named: DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints (XH, LL, SL, LD0, PZ, YJ0, XX, YD, CL, TS, YX), pp. 385–399.