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Travelled to:
1 × Denmark
1 × Germany
Collaborated with:
M.A.Reniers J.Voeten R.Jolak T.Ho-Quang M.R.V.Chaudron Sander Thuijsman Dennis Hendriks Rolf J. M. Theunissen B.v.d.Sanden M.Geilen T.Basten J.Jacobs R.Frijns S.Adyanthaya S.Stuijk M.C.W.Geilen H.Corporaal
Talks about:
base (3) effort (2) model (2) first (2) time (2) supervisori (1) lithographi (1) supervisor (1) synthesi (1) challeng (1)

Person: Ramon R. H. Schiffelers

DBLP DBLP: Schiffelers:Ramon_R=_H=

Contributed to:

MoDELS 20152015
DATE 20142014
MoDELS 20182018
CASE 20192019

Wrote 4 papers:

MoDELS-2015-SandenRGBJVS #composition #design #modelling
Modular model-based supervisory controller design for wafer logistics in lithography machines (BvdS, MAR, MG, TB, JJ, JV, RRHS), pp. 416–425.
DATE-2014-FrijnsASVGSC #analysis #graph
Timing analysis of First-Come First-Served scheduled interval-timed Directed Acyclic Graphs (RF, SA, SS, JV, MCWG, RRHS, HC), pp. 1–6.
MoDELS-2018-JolakHCS #case study #challenge #development #modelling #multi #re-engineering
Model-Based Software Engineering: A Multiple-Case Study on Challenges and Development Efforts (RJ, THQ, MRVC, RRHS), pp. 213–223.
CASE-2019-ThuijsmanHTRS #automaton #finite #synthesis
Computational Effort of BDD-based Supervisor Synthesis of Extended Finite Automata (ST, DH, RJMT, MAR, RRHS), pp. 486–493.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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