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Travelled to:
1 × France
1 × Germany
3 × USA
Collaborated with:
Q.Xu F.Yuan L.Huang J.Zhang Q.Zhang H.Zhou Z.Sun W.Jone
Talks about:
specul (3) time (3) schedul (2) placement (1) framework (1) prospect (1) approxim (1) generat (1) circuit (1) voltag (1)

Person: Rong Ye

DBLP DBLP: Ye:Rong

Contributed to:

DATE 20152015
DAC 20142014
DAC 20132013
DATE 20122012
DAC 20112011

Wrote 5 papers:

DATE-2015-YeYZX #on the
On the premises and prospects of timing speculation (RY, FY, JZ, QX), pp. 605–608.
DAC-2014-ZhangYYX #approximate #framework #named
ApproxIt: An Approximate Computing Framework for Iterative Methods (QZ, FY, RY, QX), p. 6.
DAC-2013-YeYSJX #generative
Post-placement voltage island generation for timing-speculative circuits (RY, FY, ZS, WBJ, QX), p. 6.
DATE-2012-YeYZX #scheduling
Clock skew scheduling for timing speculation (RY, FY, HZ, QX), pp. 929–934.
DAC-2011-HuangYX #multi #scheduling
Customer-aware task allocation and scheduling for multi-mode MPSoCs (LH, RY, QX), pp. 387–392.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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