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Travelled to:
1 × Canada
10 × USA
4 × France
4 × Germany
Collaborated with:
C.Lin Y.Lu J.Wang D.F.Wong Y.Chen X.Zeng R.P.Dick P.Banerjee R.Chen A.Aziz L.Shang C.Yan L.Li H.Zhu A.Xie X.Tang N.V.Shenoy W.Nicholls R.Ye F.Yuan Q.Xu A.Mallik D.Sinha Z.(.Gu I.Liu C.Feng J.Tao A.Goel K.Sajid V.Singhal Y.Zhi W.Luk F.Yang
Talks about:
optim (7) algorithm (5) under (5) effici (4) design (4) retim (4) base (4) constraint (3) crosstalk (3) schedul (3)

Person: Hai Zhou


Contributed to:

DATE 20142014
DATE 20132013
DATE 20122012
DAC 20112011
DATE 20112011
DAC 20092009
DAC 20082008
DAC 20072007
DATE 20072007
DAC 20062006
DATE 20062006
DAC 20052005
DATE v2 20042004
DATE 20032003
DAC 20012001
DAC 20002000
DAC 19991999
CAV 19981998
DAC 19981998

Wrote 25 papers:

Recovery-based resilient latency-insensitive systems (YC, XZ, HZ), pp. 1–6.
DATE-2013-ChenZ #design #optimisation
Resource-constrained high-level datapath optimization in ASIP design (YC, HZ), pp. 198–201.
DATE-2013-LuZ #constraints #fault
Retiming for Soft Error Minimization Under Error-Latching Window Constraints (YL, HZ), pp. 1008–1013.
DATE-2012-YeYZX #scheduling
Clock skew scheduling for timing speculation (RY, FY, HZ, QX), pp. 929–934.
DAC-2011-LiLZ #multi #scheduling
Optimal multi-domain clock skew scheduling (LL, YL, HZ), pp. 152–157.
DATE-2011-ChenZD #optimisation
Integrated circuit white space redistribution for temperature optimization (YC, HZ, RPD), pp. 613–618.
DATE-2011-ZhiLZYZZ #algorithm #multi #performance #scheduling
An efficient algorithm for multi-domain clock skew scheduling (YZ, WSL, HZ, CY, HZ, XZ), pp. 1364–1369.
DAC-2009-FengZYTZ #algorithm #performance
Provably good and practically efficient algorithms for CMP dummy fill (CF, HZ, CY, JT, XZ), pp. 539–544.
DAC-2009-LuSZZYZ #analysis #process #reliability #statistics
Statistical reliability analysis under process variation and aging effects (YL, LS, HZ, HZ, FY, XZ), pp. 514–519.
DAC-2009-LuZSZ #algorithm #manycore #parallel
Multicore parallel min-cost flow algorithm for CAD applications (YL, HZ, LS, XZ), pp. 832–837.
DAC-2008-WangZ #algorithm #incremental #performance
An efficient incremental algorithm for min-area retiming (JW, HZ), pp. 528–533.
DAC-2007-ChenZ #performance #process
Fast Min-Cost Buffer Insertion under Process Variations (RC, HZ), pp. 338–343.
DATE-2007-LinXZ #design #network
Design closure driven delay relaxation based on convex cost network flow (CL, AX, HZ), pp. 63–68.
DAC-2006-LinZ #algorithm #constraints #performance
An efficient retiming algorithm under setup and hold constraints (CL, HZ), pp. 945–950.
DAC-2006-WangZ #bound
Optimal jumper insertion for antenna avoidance under ratio upper-bound (JW, HZ), pp. 761–766.
DATE-2006-MallikSBZ #design #optimisation #power management
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment (AM, DS, PB, HZ), pp. 618–623.
DAC-2005-GuWDZ #behaviour #design #incremental #physics
Incremental exploration of the combined physical and behavioral design space (Z(G, JW, RPD, HZ), pp. 208–213.
DAC-2005-TangZB #library #optimisation #power management #synthesis
Leakage power optimization with dual-Vth library in high-level synthesis (XT, HZ, PB), pp. 202–207.
DATE-v2-2004-LinZ #fixpoint
Wire Retiming for System-on-Chip by Fixpoint Computation (CL, HZ), pp. 1092–1097.
DATE-2003-Zhou #verification
Timing Verification with Crosstalk for Transparently Latched Circuits (HZ), pp. 10056–10061.
DAC-2001-ZhouSN #analysis #fixpoint
Timing Analysis with Crosstalk as Fixpoints on Complete Lattice (HZ, NVS, WN), pp. 714–719.
DAC-2000-ZhouW #composition #power management
Optimal low power X OR gate decomposition (HZ, DFW), pp. 104–107.
DAC-1999-ZhouWLA #strict
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations (HZ, DFW, IML, AA), pp. 96–99.
CAV-1998-GoelSZAS #formal method #similarity
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions (AG, KS, HZ, AA, VS), pp. 244–255.
DAC-1998-ZhouW #constraints
Global Routing with Crosstalk Constraints (HZ, DFW), pp. 374–377.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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