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Travelled to:
2 × USA
Collaborated with:
F.N.Najm K.R.Heloue F.Taraporevala J.Liu
Talks about:
corner (2) cover (2) time (2) all (2) approach (1) process (1) analysi (1) static (1) wires (1) optim (1)

Person: Sari Onaissi

DBLP DBLP: Onaissi:Sari

Contributed to:

DAC 20112011
DAC 20092009

Wrote 2 papers:

DAC-2011-OnaissiTLN #analysis #approach #performance
A fast approach for static timing analysis covering all PVT corners (SO, FT, JL, FNN), pp. 777–782.
DAC-2009-OnaissiHN #optimisation #process
Clock skew optimization via wiresizing for timing sign-off covering all process corners (SO, KRH, FNN), pp. 196–201.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.