Travelled to:3 × USA
Collaborated with:F.N.Najm S.Onaissi N.Azizi
Talks about:model (2) time (2) parameter (1) arbitrari (1) process (1) general (1) current (1) analysi (1) within (1) variat (1)
Person: Khaled R. Heloue
DBLP: Heloue:Khaled_R=
Contributed to:
200920082007Wrote 3 papers:
- DAC-2009-OnaissiHN #optimisation #process
- Clock skew optimization via wiresizing for timing sign-off covering all process corners (SO, KRH, FNN), pp. 196–201.
- DAC-2008-HeloueN #analysis #modelling
- Parameterized timing analysis with general delay models and arbitrary variation sources (KRH, FNN), pp. 403–408.
- DAC-2007-HeloueAN #correlation #estimation #modelling
- Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation (KRH, NA, FNN), pp. 93–98.