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Travelled to:
2 × USA
Collaborated with:
C.Tanaka S.Murai M.Terai K.Kinoshita T.Ogihara H.Fujiwara
Talks about:
system (3) reorgan (2) logic (2) lore (2) masterslic (1) integr (1) design (1) comput (1) array (1) part (1)

Person: Shunichiro Nakamura

DBLP DBLP: Nakamura:Shunichiro

Contributed to:

DAC 19811981
DAC 19781978

Wrote 2 papers:

DAC-1981-TanakaMNOTK #array #design #logic
An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 (CT, SM, SN, TO, MT, KK), pp. 59–65.
DAC-1978-NakamuraMTTFK #logic #named
LORES — Logic Reorganization System (SN, SM, CT, MT, HF, KK), pp. 250–260.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.