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Travelled to:
1 × France
4 × USA
Collaborated with:
S.Murai Y.Higami T.Ogihara H.Fujiwara C.Tanaka S.Nakamura M.Terai S.Kajihara I.Pomeranz S.M.Reddy Y.Takamatsu
Talks about:
system (3) design (3) logic (3) reorgan (2) generat (2) circuit (2) test (2) scan (2) lore (2) masterslic (1)

Person: Kozo Kinoshita

DBLP DBLP: Kinoshita:Kozo

Contributed to:

ED&TC 19971997
DAC 19931993
DAC 19831983
DAC 19811981
DAC 19781978

Wrote 5 papers:

EDTC-1997-HigamiK #design #parallel
Design of partially parallel scan chain (YH, KK), p. 626.
DAC-1993-KajiharaPKR #effectiveness #fault #generative #logic #testing
Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits (SK, IP, KK, SMR), pp. 102–106.
DAC-1983-OgiharaMTKF #bidirectional #design #generative #testing
Test generation for scan design circuits with tri-state modules and bidirectional terminals (TO, SM, YT, KK, HF), pp. 71–78.
DAC-1981-TanakaMNOTK #array #design #logic
An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 (CT, SM, SN, TO, MT, KK), pp. 59–65.
DAC-1978-NakamuraMTTFK #logic #named
LORES — Logic Reorganization System (SN, SM, CT, MT, HF, KK), pp. 250–260.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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