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Travelled to:
6 × USA
Collaborated with:
T.Ogihara C.Tanaka K.Kinoshita M.Terai H.Fujiwara H.Toyoshima S.Saruyama S.Nakamura H.Tsuji K.Muroi G.Yonemori Y.Takamatsu M.Kakinuma K.Sakaguchi T.Yahara K.Okazaki R.Katoh M.Tachibana
Talks about:
system (8) design (5) generat (3) circuit (3) test (3) scan (3) gate (3) masterslic (2) reorgan (2) integr (2)

Person: Shinichi Murai

DBLP DBLP: Murai:Shinichi

Contributed to:

DAC 19891989
DAC 19871987
DAC 19851985
DAC 19831983
DAC 19811981
DAC 19791979
DAC 19781978

Wrote 8 papers:

DAC-1989-OgiharaMYM #effectiveness #generative #named #reliability #testing
MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits (TO, KM, GY, SM), pp. 519–524.
DAC-1987-OgiharaTM #design #named
ASTA: LSI Design Management System (TO, HT, SM), pp. 530–536.
DAC-1985-OgiharaSM #automation #generative #named #parametricity #testing
PATEGE: an automatic DC parametric test generation system for series gated ECL circuits (TO, SS, SM), pp. 212–218.
DAC-1983-OgiharaMTKF #bidirectional #design #generative #testing
Test generation for scan design circuits with tri-state modules and bidirectional terminals (TO, SM, YT, KK, HF), pp. 71–78.
DAC-1981-TanakaMNOTK #array #design #logic
An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 (CT, SM, SN, TO, MT, KK), pp. 59–65.
DAC-1981-TanakaMTYOTKT #array #design #layout
An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 (CT, SM, HT, TY, KO, MT, RK, MT), pp. 812–819.
A hierarchical placement procedure with a simple blocking scheme (SM, HT, MK, KS, CT), pp. 18–23.
DAC-1978-NakamuraMTTFK #logic #named
LORES — Logic Reorganization System (SN, SM, CT, MT, HF, KK), pp. 250–260.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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