Travelled to:1 × France
3 × Germany
4 × USA
Collaborated with:T.Yoneda I.Polian E.Gizdarski S.Murai K.Kinoshita H.Iwata M.Imanishi K.Masuda S.Ohtake K.Ohtani T.Ogihara Y.Takamatsu S.Nakamura C.Tanaka M.Terai
Talks about:test (7) generat (3) algorithm (2) function (2) wrapper (2) schedul (2) method (2) fault (2) delay (2) scan (2)
Person: Hideo Fujiwara
DBLP: Fujiwara:Hideo
Contributed to:
2008
2007200720062003200119831978Wrote 9 papers:
- DATE-2008-YonedaF #functional #reuse
- Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects (TY, HF), pp. 1366–1369.
- DAC-2007-IwataYF
- A DFT Method for Time Expansion Model at Register Transfer Level (HI, TY, HF), pp. 682–687.
- DATE-2007-YonedaIF #algorithm #configuration management #interactive #scheduling #using
- Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers (TY, MI, HF), pp. 231–236.
- DATE-2006-PolianF #constraints #functional #testing
- Functional constraints vs. test compression in scan-based delay testing (IP, HF), pp. 1039–1044.
- DATE-2006-YonedaMF #multi #scheduling
- Power-constrained test scheduling for multi-clock domain SoCs (TY, KM, HF), pp. 297–302.
- DATE-2003-OhtakeOF #algorithm #fault #generative #testing #using
- A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms (SO, KO, HF), pp. 10310–10315.
- DAC-2001-GizdarskiF #complexity #framework #learning
- A Framework for Low Complexity Static Learning (EG, HF), pp. 546–549.
- DAC-1983-OgiharaMTKF #bidirectional #design #generative #testing
- Test generation for scan design circuits with tri-state modules and bidirectional terminals (TO, SM, YT, KK, HF), pp. 71–78.
- DAC-1978-NakamuraMTTFK #logic #named
- LORES — Logic Reorganization System (SN, SM, CT, MT, HF, KK), pp. 250–260.