Travelled to:3 × USA
Collaborated with:S.Murai M.Terai S.Nakamura K.Kinoshita H.Tsuji M.Kakinuma K.Sakaguchi T.Ogihara H.Fujiwara T.Yahara K.Okazaki R.Katoh M.Tachibana
Talks about:system (5) design (3) masterslic (2) reorgan (2) integr (2) comput (2) logic (2) array (2) part (2) lore (2)
Person: Chiyoji Tanaka
DBLP: Tanaka:Chiyoji
Contributed to:
198119791978Wrote 4 papers:
- DAC-1981-TanakaMNOTK #array #design #logic
- An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 (CT, SM, SN, TO, MT, KK), pp. 59–65.
- DAC-1981-TanakaMTYOTKT #array #design #layout
- An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 (CT, SM, HT, TY, KO, MT, RK, MT), pp. 812–819.
- DAC-1979-MuraiTKST
- A hierarchical placement procedure with a simple blocking scheme (SM, HT, MK, KS, CT), pp. 18–23.
- DAC-1978-NakamuraMTTFK #logic #named
- LORES — Logic Reorganization System (SN, SM, CT, MT, HF, KK), pp. 250–260.