BibSLEIGH corpus
BibSLEIGH tags
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BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
2 × France
2 × Germany
2 × USA
Collaborated with:
S.Yoo H.Park D.Kim Y.Kim J.H.Ahn S.Lee J.Yun E.Park H.Li Y.Choi H.Lee J.Kim S.J.Hong E.Park J.Ahn S.Hong M.Son K.Kim H.Kim D.Kim J.Kim S.Kwon H.Jung J.Chung D.Kim D.H.Woo
Talks about:
memori (5) phase (4) perform (3) write (3) chang (3) main (3) cach (3) base (3) ram (3) low (3)

Person: Sunggu Lee

DBLP DBLP: Lee:Sunggu

Contributed to:

DATE 20152015
DATE 20142014
DAC 20122012
DATE 20122012
DAC 20112011
DATE 20112011
SAC 20002000

Wrote 13 papers:

DATE-2015-ParkAHYL #big data #energy #gpu #low cost #memory management #performance
Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processing (EP, JA, SH, SY, SL), pp. 1341–1346.
DATE-2015-SonLKYL #smarttech
A small non-volatile write buffer to reduce storage writes in smartphones (MS, SL, KK, SY, SL), pp. 713–718.
DATE-2014-KimKKYL #design
Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs (HK, DK, JJK, SY, SL), pp. 1–6.
DATE-2014-ParkYLL #graph #memory management #representation
Accelerating graph computation with racetrack memory and pointer-assisted graph representation (EP, SY, SL, HL), pp. 1–4.
DAC-2012-KimLCKWYL #cpu #gpu #hybrid #in memory #memory management
Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU (DK, SL, JC, DK, DHW, SY, SL), pp. 888–896.
DAC-2012-KimYL #latency #performance #ram
Write performance improvement by hiding R drift latency in phase-change RAM (YK, SY, SL), pp. 897–906.
DATE-2012-KwonKKYL #case study #in memory #memory management #ram
A case study on the application of real phase-change RAM to main memory subsystem (SK, DK, YK, SY, SL), pp. 264–267.
DATE-2012-YunLY #ram
Bloom filter-based dynamic wear leveling for phase-change RAM (JY, SL, SY), pp. 1513–1518.
DAC-2011-ChoiYLA #behaviour #fault #performance
Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache (YGC, SY, SL, JHA), pp. 978–983.
DAC-2011-ParkYL #hybrid #in memory #memory management #power management
Power management of hybrid DRAM/PRAM-based main memory (HP, SY, SL), pp. 59–64.
DATE-2011-KimYLAJ #3d #analysis #embedded #mobile #performance
A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC (DK, SY, SL, JHA, HJ), pp. 1333–1338.
DATE-2011-ParkYL #novel #power management
A novel tag access scheme for low power L2 cache (HP, SY, SL), pp. 655–660.
SAC-2000-LeeKHL #dependence #graph #scheduling #using
Task Scheduling using a Block Dependency DAG for Block-Oriented Sparse Cholesky Factorization (HL, JK, SJH, SL), pp. 641–648.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.