67 papers:
DAC-2015-LiCSHLWY #hybrid #power management- A STT-RAM-based low-power hybrid register file for GPGPUs (GL, XC, GS, HH, YL, YW, HY), p. 6.
STOC-2015-CanettiH0V #obfuscation #ram #source code- Succinct Garbling and Indistinguishability Obfuscation for RAM Programs (RC, JH, AJ, VV), pp. 429–437.
- STOC-2015-GargLOS #ram
- Garbled RAM From One-Way Functions (SG, SL, RO, AS), pp. 449–458.
ASPLOS-2015-FletcherRKDD #ram #recursion #verification- Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM (CWF, LR, AK, MvD, SD), pp. 103–116.
CGO-2015-PallisterEH #embedded #energy #optimisation #trade-off- Optimizing the flash-RAM energy trade-off in deeply embedded systems (JP, KE, SJH), pp. 115–124.
- DAC-2014-EkenZWJLC #self
- A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability (EE, YZ, WW, RVJ, HL, YC), p. 6.
- DAC-2014-SamavatianAAS #architecture #performance
- An Efficient STT-RAM Last Level Cache Architecture for GPUs (MHS, HA, MA, HSA), p. 6.
- DAC-2014-WenZMC #design #memory management #strict
- State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System (WW, YZ, MM, YC), p. 6.
ICALP-v1-2014-AfshaniCT #ram- Deterministic Rectangle Enclosure and Offline Dominance Reporting on the RAM (PA, TMC, KT), pp. 77–88.
HPCA-2014-AhnYC #architecture #named #predict- DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture (JA, SY, KC), pp. 25–36.
- HPCA-2014-FletcherRYDKD #information management #performance #ram #trade-off
- Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs (CWF, LR, XY, MvD, OK, SD), pp. 213–224.
- HPCA-2014-WangJXSX #adaptation #hybrid #migration #policy
- Adaptive placement and migration policy for an STT-RAM-based hybrid cache (ZW, DAJ, CX, GS, YX), pp. 13–24.
- DAC-2013-XuNMJX #comprehension #design #memory management #multi #trade-off
- Understanding the trade-offs in multi-level cell ReRAM memory design (CX, DN, NM, NPJ, YX), p. 6.
DATE-2013-BiWL #design- STT-RAM designs supporting dual-port accesses (XB, MAW, HL), pp. 853–858.
- DATE-2013-LiSLXCX #adaptation
- Cache coherence enabled adaptive refresh for volatile STT-RAM (JL, LS, QL, CJX, YC, YX), pp. 1247–1250.
- DATE-2013-LorenteVSPCLD #power management #ram
- Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes (VL, AV, JS, SP, RC, PL, JD), pp. 83–88.
- DATE-2013-WangDX #named #policy
- OAP: an obstruction-aware cache management policy for STT-RAM last-level caches (JW, XD, YX), pp. 847–852.
- DATE-2013-WangW #named #performance #ram
- TreeFTL: efficient RAM management for high performance of NAND flash-based storage systems (CW, WFW), pp. 374–379.
- STOC-2013-Ajtai #bound #quantifier
- Lower bounds for RAMs and quantifier elimination (MA), pp. 803–812.
ICML-c2-2013-GolovinSMY #learning #ram #scalability- Large-Scale Learning with Less RAM via Randomization (DG, DS, HBM, MY), pp. 325–333.
- HPCA-2013-ChangRLJ #comparison #energy #scalability
- Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM (MTC, PR, SLL, BJ), pp. 143–154.
- DAC-2012-HuangCK #memory management #ram
- Joint management of RAM and flash memory with access pattern considerations (PCH, YHC, TWK), pp. 882–887.
- DAC-2012-JogMXXNID #architecture #performance
- Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs (AJ, AKM, CX, YX, VN, RI, CRD), pp. 243–252.
- DAC-2012-KimYL #latency #performance #ram
- Write performance improvement by hiding R drift latency in phase-change RAM (YK, SY, SL), pp. 897–906.
- DAC-2012-WenZCWX #analysis #named #performance #reliability #scalability #statistics
- PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method (WW, YZ, YC, YW, YX), pp. 1191–1196.
- DATE-2012-KwonKKYL #case study #in memory #memory management #ram
- A case study on the application of real phase-change RAM to main memory subsystem (SK, DK, YK, SY, SL), pp. 264–267.
- DATE-2012-YunLY #ram
- Bloom filter-based dynamic wear leveling for phase-change RAM (JY, SL, SY), pp. 1513–1518.
- DATE-2012-ZhangWLJC #design #symmetry
- Asymmetry of MTJ switching and its implication to STT-RAM designs (YZ, XW, YL, AKJ, YC), pp. 1313–1318.
SIGMOD-2012-KimPSLDC #clustering #distributed #named #performance #ram #scalability- CloudRAMSort: fast and efficient large-scale distributed RAM sort on shared-nothing cluster (CK, JP, NS, HL, PD, JC), pp. 841–850.
SLE-2012-AbedBSYAK #aspect-oriented #design #multi #named- TouchRAM: A Multitouch-Enabled Tool for Aspect-Oriented Software Design (WAA, VB, MS, EY, OA, JK), pp. 275–285.
LCTES-2012-LiZXH #embedded #hybrid- Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache (QL, MZ, CJX, YH), pp. 109–118.
- DATE-2011-ChenLCP #3d #design #memory management #named
- 3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers (YCC, HL, YC, REP), pp. 583–586.
- SIGMOD-2011-DebnathSL #named #ram
- SkimpyStash: RAM space skimpy key-value store on flash-based storage (BKD, SS, JL), pp. 25–36.
- ICALP-v2-2011-GoodrichM #outsourcing #privacy #ram #simulation
- Privacy-Preserving Access of Outsourced Data via Oblivious RAM Simulation (MTG, MM), pp. 576–587.
- HPCA-2011-SmullenMNGS #energy #performance
- Relaxing non-volatility for fast and energy-efficient STT-RAM caches (CWSI, VM, AN, SG, MRS), pp. 50–61.
SOSP-2011-OngaroRSOR #performance- Fast crash recovery in RAMCloud (DO, SMR, RS, JKO, MR), pp. 29–41.
- DATE-2010-ChenLWZXZ #memory management #random #self
- A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) (YC, HL, XW, WZ, WX, TZ), pp. 148–153.
- STOC-2010-Ajtai
- Oblivious RAMs without cryptogrpahic assumptions (MA), pp. 181–190.
- LCTES-2009-YangCR #ram #stack
- Eliminating the call stack to save RAM (XY, NC, JR), pp. 60–69.
- DAC-2008-DongWSXLC #3d #architecture #evaluation #memory management #ram
- Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement (XD, XW, GS, YX, HHL, YC), pp. 554–559.
SAC-2008-ParkLLP #architecture #file system #hybrid #memory management #named #ram #scalability- PFFS: a scalable flash memory file system for the hybrid architecture of phase-change RAM and NAND flash (YP, SHL, CL, KHP), pp. 1498–1503.
PLDI-2007-CoopriderR #ram- Offline compression for on-chip ram (NC, JR), pp. 363–372.
- DAC-2006-PanCHCLCLLHWLLTYMCCPHCH #ram
- A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications (JSP, HCC, BYH, HCC, RL, CHC, YCL, CL, LH, CLW, MHL, CYL, SNT, JNY, CPM, YC, SHC, HCP, PCH, BC, AH), pp. 290–291.
- DATE-2006-TsengLC #2d #using
- A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap (TWT, JFL, DMC), pp. 53–58.
- DATE-2005-BodeanBL #ram #self
- New Schemes for Self-Testing RAM (GB, DB, AL), pp. 858–859.
- DATE-2003-SchanstraG #ram #test coverage
- Consequences of RAM Bitline Twisting for Test Coverage (IS, AJvdG), pp. 11176–11177.
PPoPP-2003-FraguelaRFPT #memory management #parallel #programming- Programming the FlexRAM parallel intelligent memory system (BBF, JR, PF, DAP, JT), pp. 49–60.
- ICALP-2000-Hagerup #ram #word
- Improved Shortest Paths on the Word RAM (TH), pp. 61–72.
HPDC-2000-XiaoZK #clustering #memory management #migration #network #ram- Incorporating Job Migration and Network RAM to Share Cluster Memory Resources (LX, XZ, SAK), pp. 71–78.
- DATE-1999-ChakrabortyGBKM #design #physics #self
- A Physical Design Tool for Built-in Self-Repairable Static RAMs (KC, AG, MB, SK, PM), p. 714–?.
- DATE-1999-HellebrandWY #symmetry
- Symmetric Transparent BIST for RAMs (SH, HJW, VNY), pp. 702–707.
- STOC-1999-Ajtai #linear #nondeterminism
- Determinism versus Non-Determinism for Linear Time RAMs (Extended Abstract) (MA), pp. 632–641.
- DATE-1998-RenovellPFZ #approach #configuration management #logic
- RAM-Based FPGA’s: A Test Approach for the Configurable Logic (MR, JMP, JF, YZ), pp. 82–88.
- DATE-1998-YarmolikHW #performance #self
- Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs (VNY, SH, HJW), pp. 173–179.
- ICALP-1998-Hagerup #performance #ram
- Simpler and Faster Dictionaries on the AC0 RAM (TH), pp. 79–90.
- EDTC-1997-ChakrabortyM #bound #functional #parallel #programmable #testing
- A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs (KC, PM), pp. 330–334.
- ICALP-1996-Miltersen #bound #multi
- Lower Bounds for Static Dictionaries on RAMs with Bit Operations But No Multiplication (PBM), pp. 442–453.
- DAC-1995-ChandnaKBRS #compilation #ram
- The Aurora RAM Compiler (AC, CDK, RBB, MR, KAS), pp. 261–266.
- STOC-1992-SimonS #complexity #on the #ram #set
- On the Complexity of RAM with Various Operation Sets (JS, MS), pp. 624–631.
- STOC-1990-Ostrovsky #performance
- Efficient Computation on Oblivious RAMs (RO), pp. 514–523.
- ICALP-1990-Wiedermann #metric #normalisation #problem #ram
- Normalizing and Accelerating RAM Computations and the Problem of Reasonable Space Measures (JW), pp. 125–138.
CSL-1990-GrandjeanR #memory management #ram #robust- RAM with Compact Memory: A Realistic and Robust Model of Computation (EG, JMR), pp. 195–233.
- DAC-1989-HemmadyR #on the
- On the Repair of Redundant RAMs (VGH, SMR), pp. 710–713.
VLDB-1989-CopelandKKS #ram- The Case For Safe RAM (GPC, TWK, RK, MGS), pp. 327–335.
- STOC-1987-Goldreich #formal method #simulation #towards
- Towards a Theory of Software Protection and Simulation by Oblivious RAMs (OG), pp. 182–194.
- ICALP-1986-DymondR #context-free grammar #memory management #parallel #recognition
- Parallel RAMs with Owned Global Memory and Deterministic Context-Free Language Recognition (Extended Abstract) (PWD, WLR), pp. 95–104.
- STOC-1982-CookD #bound #parallel #ram
- Bounds on the Time for Parallel RAM’s to Compute Simple Functions (SAC, CD), pp. 231–233.
