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Travelled to:
1 × Germany
Collaborated with:
F.Yang X.Zeng Y.Su
Talks about:
transistor (1) macromodel (1) nonlinear (1) piecewis (1) approach (1) circuit (1) reduct (1) linear (1) effici (1) order (1)

Person: Xiaoda Pan

DBLP DBLP: Pan:Xiaoda

Contributed to:

DATE 20102010

Wrote 1 papers:

DATE-2010-PanYZS #approach #megamodelling #order #performance #reduction
An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits (XP, FY, XZ, YS), pp. 1673–1676.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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