BibSLEIGH — Xuan

Travelled to:

3 × Germany
4 × France
7 × USA

Collaborated with:

F.Yang H.Zhou Y.Su C.Chiang D.Zhou C.Fang X.Li H.Zhu C.Yan W.Cai X.Liu Y.Zhang G.K.Yeap Y.Lu L.Shang Q.Huang L.Feng Y.Chen J.Tao W.Luk X.Pan J.Guo S.Sinha C.Feng J.Xue Q.Fang C.Gu Y.Zhi C.Chu J.Sun X.Zhou J.Liu R.Li Y.Wang J.Tong J.Ni

Talks about:

effici (7) model (6) circuit (5) algorithm (4) reduct (4) method (4) order (4) base (4) nonlinear (3) bayesian (3)

Person: Xuan Zeng

DBLP: Zeng:Xuan

Contributed to:

2015

2014

2012

2011

2010

2009

2008

2007

2006

2004

Wrote 18 papers:

DAC-2015-HuangFYZL #estimation #multi #performance: Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits (QH, CF, FY, XZ, XL), p. 6.
DATE-2015-FangHYZLG #estimation #fault #performance: Efficient bit error rate estimation for high-speed link by Bayesian model fusion (CF, QH, FY, XZ, XL, CG), pp. 1024–1029.
DAC-2014-FangYZL #estimation #named #performance: BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits (CF, FY, XZ, XL), p. 6.
DATE-2014-ChenZZ: Recovery-based resilient latency-insensitive systems (YC, XZ, HZ), pp. 1–6.
DAC-2012-GuoYSCZ #classification #distance #metric: Improved tangent space based distance metric for accurate lithographic hotspot classification (JG, FY, SS, CC, XZ), pp. 1173–1178.
DAC-2012-SuYZ #named #order #performance #reduction: AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits (YS, FY, XZ), pp. 295–300.
DAC-2011-LiuZYZ #3d #algorithm: An integrated algorithm for 3D-IC TSV assignment (XL, YZ, GKY, XZ), pp. 652–657.
DATE-2011-ZhiLZYZZ #algorithm #multi #performance #scheduling: An efficient algorithm for multi-domain clock skew scheduling (YZ, WSL, HZ, CY, HZ, XZ), pp. 1364–1369.
DAC-2010-LiuZYCSZ #design: Global routing and track assignment for flip-chip designs (XL, YZ, GKY, CC, JS, XZ), pp. 90–93.
DATE-2010-PanYZS #approach #megamodelling #order #performance #reduction: An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits (XP, FY, XZ, YS), pp. 1673–1676.
DAC-2009-FengZYTZ #algorithm #performance: Provably good and practically efficient algorithms for CMP dummy fill (CF, HZ, CY, JT, XZ), pp. 539–544.
DAC-2009-LuSZZYZ #analysis #process #reliability #statistics: Statistical reliability analysis under process variation and aging effects (YL, LS, HZ, HZ, FY, XZ), pp. 514–519.
DAC-2009-LuZSZ #algorithm #manycore #parallel: Multicore parallel min-cost flow algorithm for CAD applications (YL, HZ, LS, XZ), pp. 832–837.
DAC-2008-WangLZTYTCN #scheduling: Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays (YW, WSL, XZ, JT, CY, JT, WC, JN), pp. 223–226.
DATE-2007-ZhuZCXZ #grid #probability #process: A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology (HZ, XZ, WC, JX, DZ), pp. 1514–1519.
DATE-2006-ZengFSCZC #domain model #order #reduction: Time domain model order reduction by wavelet collocation method (XZ, LF, YS, WC, DZ, CC), pp. 21–26.
DATE-v2-2004-FengZCZF #analysis #order #reduction: Direct Nonlinear Order Reduction with Variational Analysis (LF, XZ, CC, DZ, QF), pp. 1316–1321.
DATE-v2-2004-ZhouZLLZC #analysis #using: Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method (XZ, DZ, JL, RL, XZ, CC), pp. 1322–1326.