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Travelled to:
1 × USA
Collaborated with:
S.A.Szygenda E.S.Fehr G.E.Ott S.Kang
Talks about:
processor (1) parallel (1) massiv (1) design (1) simul (1) logic (1) fault (1) error (1) array (1)

Person: Youngmin Hur

DBLP DBLP: Hur:Youngmin

Contributed to:

HPCA 19951995

Wrote 1 papers:

HPCA-1995-HurSFOK #array #design #fault #logic #parallel #simulation
Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation (YH, SAS, ESF, GEO, SK), pp. 340–347.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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