Travelled to:1 × Germany
3 × USA
Collaborated with:∅ W.M.v.Cleemput J.Shin H.Kim Y.Hur S.A.Szygenda E.S.Fehr G.E.Ott
Talks about:interconnect (1) processor (1) placement (1) synthesi (1) parallel (1) descript (1) boundari (1) multipl (1) automat (1) system (1)
Person: Sungho Kang
DBLP: Kang:Sungho
Contributed to:
1999
1995
19831981Wrote 4 papers:
- DATE-1999-ShinKK #bound #multi #testing
- At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks (JS, HK, SK), p. 473–?.
- HPCA-1995-HurSFOK #array #design #fault #logic #parallel #simulation
- Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation (YH, SAS, ESF, GEO, SK), pp. 340–347.
- DAC-1983-Kang #linear
- Linear ordering and application to placement (SK), pp. 457–464.
- DAC-1981-KangC #automation #synthesis
- Automatic PLA synthesis from a DDL-P description (SK, WMvC), pp. 391–397.