Travelled to:7 × USA
Collaborated with:E.W.Thompson N.Billawala A.K.Bose A.A.Lekkos ∅ E.W.Thomson R.Pierce Y.Hur E.S.Fehr G.E.Ott S.Kang
Talks about:simul (6) digit (5) system (4) logic (4) fault (3) structur (2) level (2) multilevel (1) represent (1) processor (1)
Person: Stephen A. Szygenda
DBLP: Szygenda:Stephen_A=
Facilitated 4 volumes:
EdEdEdEdContributed to:
19951977
19761975197419731972Wrote 7 papers:
- HPCA-1995-HurSFOK #array #design #fault #logic #parallel #simulation
- Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation (YH, SAS, ESF, GEO, SK), pp. 340–347.
- DAC-1977-BoseS #detection #logic
- Detection of static and dynamic hazards in logic nets (AKB, SAS), pp. 220–224.
- ICSE-1976-BillawalaST #data type #multi #simulation
- A Data Structure and Drive Mechanism for a Table-Driven Simulation System Employing Multilevel Structural Representations of Digital Systems (NB, SAS, EWT), pp. 151–157.
- DAC-1975-ThompsonS #fault #simulation
- Three levels of accuracy for the simulation of different fault types in digital systems (EWT, SAS), pp. 105–113.
- DAC-1974-ThompsonSBP #analysis #fault #simulation #using
- Timing analysis for digital fault simulation using assignable delays (EWT, SAS, NB, RP), pp. 266–272.
- DAC-1973-SzygendaL #functional #logic #simulation
- Integrated techniques for functional and gate-level digital logic simulation (SAS, AAL), pp. 159–172.
- DAC-1972-Szygenda #generative #logic #named #simulation #testing
- TEGAS2 — anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic (SAS), pp. 116–127.