Travelled to:1 × Germany
4 × USA
Collaborated with:∅ H.Higuchi M.Fujita P.C.McGeer R.K.Brayton K.Chen S.Muroga H.Sato Y.Yasue
Talks about:state (3) algorithm (2) transit (2) resubstitut (1) resynthesi (1) incomplet (1) synthesi (1) parallel (1) function (1) approach (1)
Person: Yusuke Matsunaga
DBLP: Matsunaga:Yusuke
Contributed to:
2014
1996199319911990Wrote 6 papers:
- DATE-2014-Matsunaga #algorithm #generative #parallel #synthesis
- Synthesis algorithm of parallel index generation units (YM), pp. 1–6.
- DAC-1996-HiguchiM #algorithm #finite #performance #reduction #state machine
- A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines (HH, YM), pp. 463–466.
- DAC-1996-Matsunaga #equivalence #performance
- An Efficient Equivalence Checker for Combinational Circuits (YM), pp. 629–634.
- DAC-1993-MatsunagaMB #on the #transitive
- On Computing the Transitive Closure of a State Transition Relation (YM, PCM, RKB), pp. 260–265.
- DAC-1991-ChenMMF #approach #network #optimisation
- A Resynthesis Approach for Network Optimization (KCC, YM, SM, MF), pp. 458–463.
- DAC-1990-SatoYMF #diagrams
- Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams (HS, YY, YM, MF), pp. 284–289.