Travelled to:1 × Germany
6 × USA
Collaborated with:K.Cheng S.Huang M.Fujita S.Muroga J.J.Lu T.Lee Y.Matsunaga C.Lin S.Chang M.Marek-Sadowska F.Lu M.K.Iyer G.Parthasarathy L.Wang
Talks about:optim (3) sequenti (2) network (2) effici (2) simul (2) logic (2) error (2) base (2) resynthesi (1) algorithm (1)
Person: Kuang-Chien Chen
DBLP: Chen:Kuang=Chien
Contributed to:
2005
199819961995199219911990Wrote 8 papers:
- DATE-2005-LuIPWCC #performance #satisfiability
- An Efficient Sequential SAT Solver With Improved Search Strategies (FL, MKI, GP, LCW, KTC, KCC), pp. 1102–1107.
- DAC-1998-HuangCCL #design #fault
- Fault-Simulation Based Design Error Diagnosis for Sequential Circuits (SYH, KTC, KCC, JYJL), pp. 632–637.
- DAC-1996-HuangCC #fault #verification
- Error Correction Based on Verification Techniques (SYH, KCC, KTC), pp. 258–261.
- DAC-1996-HuangCCL #generative #simulation
- Compact Vector Generation for Accurate Power Simulation (SYH, KCC, KTC, TCL), pp. 161–164.
- DAC-1995-LinCCMC #logic #synthesis
- Logic Synthesis for Engineering Change (CCL, KCC, SCC, MMS, KTC), pp. 647–652.
- DAC-1992-ChenF #algorithm #logic #optimisation #performance #set
- Efficient Sum-to-One Subsets Algorithm for Logic Optimization (KCC, MF), pp. 443–448.
- DAC-1991-ChenMMF #approach #network #optimisation
- A Resynthesis Approach for Network Optimization (KCC, YM, SM, MF), pp. 458–463.
- DAC-1990-ChenM #multi #network #optimisation
- Timing Optimization for Multi-Level Combinational Networks (KCC, SM), pp. 339–344.